ZiLOG eZ80 User Manual page 396

IND. Input from I/O and Decrement; an input/output instruction.
Index registers (IX and IY).
displacement addressing in memory.
INDM. Input from I/O and Decrement; an input/output instruction.
Input from I/O and Decrement with Repeat; an input/output instruction.
INDMR.
Input from I/O and Decrement with Repeat; an input/output instruction.
INDR.
Input from I/O and Decrement; an input/output instruction.
IND2.
IND2R. Input from I/O and Decrement with Repeat; an input/output instruction.
INI. Input from I/O and Increment; an input/output instruction.
Input from I/O and Increment; an input/output instruction.
INIM.
Input from I/O and Increment with Repeat; an input/output instruction.
INIMR.
Input from I/O and Increment with Repeat; an input/output instruction.
INIR.
INI2. Input from I/O and Increment; an input/output instruction.
INI2R. Input from I/O and Increment with Repeat; an input/output instruction.
INT. Interrupt.
Interrupt Acknowledge.
INTACK.
Internet Control Message Protocol.
a key part of the TCP/IP protocol suite. The packet internet gopher (ping) application is based on ICMP.
A DOD standard protocol designed for use in interconnected systems of packet-
Internet protocol (IP).
switched computer communication networks.
A suspension of a process, such as the execution of a computer program, caused by an event
interrupt.
external to that process, and performed in such a way that the process can be resumed. The three types of
interrupts include: internal hardware, external hardware, and software.
interrupt acknowledge cycle.
request.
Interrupt Enable Flag.
or reset using the Enable Interrupt (EI) and Disable Interrupt (DI) instructions.
Interrupt Page Address register (I).
table address for Mode 2 vectored interrupts.
interrupt request (IRQ).
Interrupt Service Routine.
information, or control information between the CPU and an interrupting peripheral.
interrupt vector address.
interrupt service routine.
Input from I/O on Page 0; an input/output instruction.
IN0.
Auxiliary Chip Select Output Signal.
IOCS.
I/O Request.
IORQ.
Internet Protocol.
IP.
UM007714-0908
The multibyte registers IX and IY allow standard addressing and relative
An Internet protocol that reports datagram delivery errors. ICMP is
The time required for the eZ80
®
In the eZ80 CPU, there are two interrupt enable flags, IEF1 and IEF2, that are set
The 8-bit I register stores the upper 8 bits of the interrupt vector
Hardware lines that carry a signal from a device to the processor.
An interrupt service routine can affect the exchange of data, status
The address used by the eZ80
®
CPU to respond to an interrupt service
®
CPU as the starting point for the associated
®
eZ80 CPU
User Manual
387
Glossary