ZiLOG eZ80 User Manual page 69

Table 37. Instruction Summary (Continued)
Instruction and Operation
BIT b,s
Z ← ~s[b]
CALL cc,Mmn
if cc {
(SP) ← PC
PC ← Mmn
}
CALL Mmn
(SP) ← PC
PC ← Mmn
CCF
C ← ~C
CP A,s
A – s
CPD
A–(HL)
HL ← HL – 1
BC ← BC – 1
CPDR
repeat {
A–(HL)
HL ← HL – 1
BC ← BC – 1
} while (~Z and BC ≠ 0)
Note: *This flag value is a function of the result of the affected operation.
— = No Change.
0 = Set to 0.
1 = Set to 1.
V = Set to 1 if overflow occurs.
X = Undetermined.
P = Set to the parity of the result (0 if odd parity, 1 if even parity).
IEF2 = The value of Interrupt Enable Flag 2.
UM007714-0908
Address Mode
Opcode(s)
Dest Source (Hex)
(HL)
CB 46–7E
(IX/Y+d) DD/FD CB dd
46–7E
r
CB 40–7F
C4–FC
CD
3F
(HL) BE
ir
DD/FD BC–BD
(IX/Y+d) DD/FD BE dd
n
FE
r
B8–BF
ED A9
ED B9
®
eZ80 CPU
User Manual
Flags Affected
S Z H P/V N C
X * 1 X 0 —
— — — — — —
— — — — — —
— — * — 0 *
* * * V 1 *
* * * * 1 —
* * * * 1 —
CPU Instruction Set
60