ZiLOG eZ80 User Manual page 274

OTIMR
Output to I/O and Increment
Operation
repeat {
({UU, 00h, C}) ← (HL)
B ← B – 1
C ← C+1
HL ← HL+1
} while B ≠ 0
Description
The CPU loads the contents of the memory location specified by the multibyte HL register
into CPU memory. The CPU next outputs this byte to the I/O address specified by the C
register with the High byte of the address, ADDR[15:8], forced to 0. The upper byte of the
address bus, ADDR[23:16] is undefined for I/O addresses. The B register decrements. The
C and HL registers increment. The instruction repeats until the B register equals 0.
Condition Bits Affected
S
Z
H
P/V
N
C
Attributes
Mnemonic Operand
OTIMR
OTIMR.S
OTIMR.L
UM007714-0908
Undefined.
Set if B – 1 = 0; reset otherwise.
Undefined.
Undefined.
Set if msb of data is logical 1; reset otherwise.
Undefined.
ADL Mode Cycle
— X
— 1
— 0
Opcode (hex)
2 + 3 * B ED, 93
3 + 3 * B 52, ED, 93
3 + 3 * B 49, ED, 93
®
eZ80 CPU
User Manual
265
CPU Instruction Set