ZiLOG eZ80 User Manual page 238

LD rr, (IX/Y+d)
Load Register
Operation
rr ← (IX/Y+d)
Description
The rr operand is any of the multibyte CPU registers BC, DE, or HL. The CPU writes the
contents of the memory location, specified by the contents of the IX or IY register offset
by the two's-complement displacement d, to the multibyte rr register.
Condition Bits Affected
None.
Attributes
Mnemonic Operand
LD
LD.S
LD.L
LD
LD.S
LD.L
LD
LD.S
LD.L
LD
LD.S
LD.L
LD
LD.S
LD.L
LD
LD.S
LD.L
UM007714-0908
ADL Mode Cycle Opcode (hex)
BC,(IX+d) 0/1
BC,(IX+d) 1
BC,(IX+d) 0
DE,(IX+d) 0/1
DE,(IX+d) 1
DE,(IX+d) 0
HL,(IX+d) 0/1
HL,(IX+d) 1
HL,(IX+d) 0
BC,(IY+d) 0/1
BC,(IY+d) 1
BC,(IY+d) 0
DE,(IY+d) 0/1
DE,(IY+d) 1
DE,(IY+d) 0
HL,(IY+d) 0/1
HL,(IY+d) 1
HL,(IY+d) 0
5/6
DD, 07, dd
6
52, DD, 07, dd
7
49, DD, 07, dd
5/6
DD, 17, dd
6
52, DD, 17, dd
7
49, DD, 17, dd
5/6
DD, 27, dd
6
52, DD, 27, dd
7
49, DD, 27, dd
5/6
FD, 07, dd
6
52, FD, 07, dd
7
49, FD, 07, dd
4/5
FD, 17, dd
5
52, FD, 17, dd
6
49, FD, 17, dd
4/5
FD, 27, dd
5
52, FD, 27, dd
6
49, FD, 27, dd
®
eZ80 CPU
User Manual
229
CPU Instruction Set