ZiLOG eZ80 User Manual page 265

OTD2R
Output to I/O and Decrement with Repeat
Operation
repeat {
({UU, DE[15:0]}) ← (HL)
BC ← BC – 1
DE ← DE – 1
HL ← HL – 1
} while BC ≠ 0
Description
The CPU loads the contents of the memory location specified by the multibyte HL register
into CPU memory. This byte is output to I/O address {UU, DE[15:0]}. The upper byte of
the address bus, ADDR[23:16] is undefined for I/O addresses. The BC, DE, and HL regis-
ters are decremented. The instruction repeats until the BC register equals 0.
Condition Bits Affected
S
Z
H
P/V
N
C
Attributes
Mnemonic Operand
OTD2R
OTD2R.S
OTD2R.L
Note
This instruction operates differently in eZ80190 device. In the eZ80190, operation is:
repeat {
({UU, BC[15:0]}) ← (HL)
B ← B – 1
UM007714-0908
Not affected.
Set if B C– 1 = 0; reset otherwise.
Not affected.
Not affected.
Set if msb of data is logical 1; reset otherwise.
Not affected.
ADL Mode Cycle
— X
— 1
— 0
Opcode (hex)
2 + 3 * B ED, BC
3 + 3 * B 52, ED, BC
3 + 3 * B 49, ED, BC
®
eZ80 CPU
User Manual
256
CPU Instruction Set