Table of Contents
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Interrupts
This chapter describes interrupt operation in maskable and nonmaskable mixed memory
modes.
Illegal Instruction Traps
This chapter describes the consequences of undefined operations.
I/O Space
This chapter describes input/output memory for on- and off-chip peripherals.
Addressing Modes
This chapter describes methods of accessing different addressing modes.
Mixed-Memory Mode Applications
This chapter describes the MADL control bit and mixed memory mode guidelines.
CPU Instruction Set
This chapter lists assembly language instructions, including mnemonic definitions and a
summary of the eZ80
Opcode Maps
This chapter provides a detailed diagram of each opcode segment.
Related Documents
eZ80190 eZ80190 Product Specification
eZ80L92 eZ80L92 Product Specification
eZ80F92 eZ80F92 Product Specification
eZ80F91 eZ80F91 Product Specification
Manual Conventions
The following conventions are used to provide clarity in the document.
UM007714-0908
®
CPU instruction set.
eZ80190 Module Product Specification
eZ80L92 Module Product Specification
eZ80F92 Ethernet Module Product Specification
eZ80F92 Flash Module Product Specification
eZ80F91 Module Product Specification
®
eZ80
CPU
User Manual
PS0066
PS0191
PS0130
PS0170
PS0153
PS0186
PS0189
PS0192
PS0193
Manual Objectives
vii
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