ZiLOG eZ80 User Manual page 281

OUTD2
Output to I/O and Decrement
Operation
({UU, BC[15:0]}) ← (HL)
B ← B – 1
C ← C – 1
HL ← HL – 1
Description
The CPU loads the contents of the memory location specified by the multibyte HL register
into CPU memory. The CPU next outputs this byte to I/O address {UU, BC[15:0]}. The
upper byte of the address bus, ADDR[23:16] is undefined for I/O addresses. The B, C, and
HL registers decrement.
Condition Bits Affected
S
Z
H
P/V
N
C
Attributes
Mnemonic Operand
OUTD2
OUTD2.S
OUTD2.L
UM007714-0908
Not affected.
Set if B – 1 = 0; reset otherwise.
Not affected.
Not affected.
Set if msb of data is logical 1; reset otherwise.
Not affected.
ADL Mode Cycle Opcode (hex)
— X
— 1
— 0
5
ED, AC
6
52, ED, AC
6
49, ED, AC
®
eZ80 CPU
User Manual
272
CPU Instruction Set