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Table 37. Instruction Summary (Continued)
Instruction and Operation
CPI
A–(HL)
HL ← HL+1
BC ← BC – 1
CPIR
repeat {
A–(HL)
HL ← HL+1
BC ← BC – 1
} while (~Z and BC ≠ 0)
CPL
A ← ~A
DAA
A ← decimal adjust (A)
DEC ss
ss ← ss – 1
DI
IEF1,2 ← 0
DJNZ d
B ← B – 1
if B ≠ 0 {
PC ← PC+d
}
EI
IEF1,2 ← 1
Note: *This flag value is a function of the result of the affected operation.
— = No Change.
0 = Set to 0.
1 = Set to 1.
V = Set to 1 if overflow occurs.
X = Undetermined.
P = Set to the parity of the result (0 if odd parity, 1 if even parity).
IEF2 = The value of Interrupt Enable Flag 2.
UM007714-0908
Address Mode
Opcode(s)
Dest Source
(Hex)
ED A1
ED B1
2F
27
(HL)
35
ir
DD/FD 25–2D
IX/Y
DD/FD 2B
(IX/Y+d)
DD/FD 35 dd
r
05–3D
rr
0B–2B
SP
3B
F3
10 dd
FB
®
eZ80
CPU
User Manual
Flags Affected
S
Z
H P/V N
C
*
*
*
*
1
—
*
*
*
*
1
—
— —
1
—
1
—
*
*
*
P
—
*
*
*
*
V
1
—
*
*
*
V
1
—
— — —
—
— —
*
*
*
V
1
—
*
*
*
V
1
—
— — —
—
— —
— — —
—
— —
— — —
—
— —
— — —
—
— —
— — —
—
— —
CPU Instruction Set
61
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