Single-Instruction Memory Mode Changes - ZiLOG eZ80 User Manual

Single-Instruction Memory Mode Changes

Often, the CPU must perform a single operation using the memory mode opposite from
that currently set by the ADL mode bit. The CPU is capable of changing between ADL
mode and Z80 mode for a single instruction. Certain CPU instructions can be appended
with the memory mode opcode suffixes .SIS, .LIL, .LIS, and .SIL to indicate that a par-
ticular memory mode is appropriate for this instruction only. The following three exam-
ples serve to make the suffix operation for single-instruction memory mode changes more
clear.
Suffix Example 1: LD HL, Mmn in
In mode (ADL mode bit = 0), only two bytes of immediate data are normally fetched
Z80
and the upper byte of all CPU multibyte registers is undefined. Compare the operation of
the following lines of code to observe the effect of the opcode suffixes.
.ASSUME ADL = 0
LD HL, 3456h
LD HL, 123456h
LD.SIS HL, 3456h
LD.LIL HL, 123456h
LD.LIS HL, 3456h
LD.SIL HL, 123456h
In all cases of Suffix Example 1, the memory mode is unchanged after the operation, as it
remains in Z80 mode (ADL mode bit = 0) following completion of each instruction. How-
ever, during operation of the LD.LIS, LD.LIL, and LD.SIL instructions, all or parts of
the CPU function temporarily in ADL mode. The .IL segment of the suffix forces the con-
trol block, to operate in ADL mode. The .L segment of the suffix forces the data block to
operate in ADL mode.
UM007714-0908
Mode
Z80
;Z80 mode operation is default.
;HL[23:0] ¨ {00h, 3456h}.
;Invalid–Z80 mode cannot load 24-;bit value.
;Same as LD HL, 3456, because
;ADL = 0. HL[23:0] ¨ {00h, 3456h}.
;.IS directs eZ80 to fetch only
;16 bits of data.
;.S forces upper byte of HL
;register to an undefined state.
;HL[23:0] ¨ 123456h.
;.IL directs eZ80 to fetch 24-
;bits of data.
;.L uses all 3 bytes of HL
;register.
;HL[23:0] ¨ {00h, 3456h}. .IS
;directs eZ80 to fetch only 16-
;bits of data. .L uses all 3 bytes
;of HL register.
;HL[23:0] ¨ {00h, 3456h}.
;.IL directs eZ80 to fetch 24 bits
;of data. .S forces upper byte of
;HL register to an undefined
;state because registers are
;defined to be only 16-bits.
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eZ80 CPU
User Manual
Memory Mode Switching
20