ZiLOG eZ80 User Manual page 14

Clock
Address
Data In
Command
Execution
State
INC A
LD (1234h), A
LD (5678h), A
INC A
Data Out
INST_READ
MEM_READ
MEM_WRITE
Note: F & D = Fetch & Decode
UM007714-0908
PC PC+1 PC+2 PC+3
3Ch 32h 34h 12h
INC A LD (nn), A nL nH
1 clock delay for execution
Fetch Decode Execute
Prefetch F & D F & D
Prefetch
Invalid
Figure 3. Pipeline Example
PC+4 PC+5 PC+6
1234h
32h (1234h) 78h 56h
LD (nn), A Write nL nH
Next command
1 clock delay for execution
Decode Execute
F & D F & D
Valid Invalid
®
eZ80
User Manual
PC+7
5678h
3Ch (5678h)
INC A Write
Next command
Decode Execute
Prefetch
Valid
Architectural Overview
CPU
5