ZiLOG eZ80 User Manual page 227

LD (Mmn), rr
Load Indirect
Operation
(Mmn) ← rr
Description
The rr operand is any of the multibyte registers BC, DE, or HL. The CPU stores the con-
tents of the multibyte register rr in the memory location specified by Mmn.
Condition Bits Affected
None.
Attributes
Mnemonic Operand
LD
LD
LD.SIS
LD.LIL
LD
LD
LD.SIS
LD.LIL
LD
LD
LD.SIS
LD.LIL
Note:
Zilog recommends against using the .SIL and .LIS suffixes with this instruction. The .SIL
instruction fetches a 24-bit value, Mmn. However, this instruction ignores the upper byte
and uses address {MBASE, mm, nn} instead. The .LIS instruction fetches a 16-bit value,
mn. However, the .LIS instruction does not use the MBASE value. Instead, it uses address
{00, mm, nn}.
UM007714-0908
ADL
Mode Cycle Opcode (hex)
0 6
(mn),BC
(Mmn),BC 1 8
1 7
(mn),BC
(Mmn),BC 0 9
0 6
(mn),DE
(Mmn),DE 1 8
1 7
(mn),DE
(Mmn),DE 0 9
0 5
(mn),HL
(Mmn),HL 1 7
1 6
(mn),HL
(Mmn),HL 0 8
ED, 43, nn, mm
ED, 43, nn, mm, MM
40, ED, 43, nn, mm
5B, ED, 43, nn, mm, MM
ED, 53, nn, mm
ED, 53, nn, mm, MM
40, ED, 53, nn, mm
5B, ED, 53, nn, mm, MM
22, nn, mm
22, nn, mm, MM
40, 22, nn, mm
5B, 22, nn, mm, MM
®
eZ80 CPU
User Manual
218
CPU Instruction Set