ZiLOG eZ80 User Manual page 273

OTIM
Output to I/O and Increment
Operation
({UU, 00h,C}) ← (HL)
B ← B – 1
C ← C+1
HL ← HL+1
Description
The CPU loads the contents of the memory location specified by the multibyte HL register
into CPU memory. The CPU next outputs this byte to the I/O address specified by the C
register with the High byte of the address, ADDR[15:8], forced to 0. The upper byte of the
address bus, ADDR[23:16] is undefined for I/O addresses. The B register decrements. The
C and HL registers increment.
Condition Bits Affected
S
Z
H
P/V
N
C
Attributes
Mnemonic Operand
OTIM
OTIM.S
OTIM.L
UM007714-0908
Undefined.
Set if B – 1 = 0; reset otherwise.
Undefined.
Undefined.
Set if msb of data is logical 1; reset otherwise.
Undefined.
ADL Mode Cycle Opcode (hex)
— X
— 1
— 0
5
ED, 83
6
52, ED, 83
6
49, ED, 83
®
eZ80 CPU
User Manual
264
CPU Instruction Set