Ez80 Cpu Registers In Adl Mode - ZiLOG eZ80 User Manual

Table 2. CPU Control Registers and Bit Flags in Z80 Mode
8-Bit
Registers
I
MBASE
R
Individual 8-Bit Registers
IXH
IYH
®
eZ80 CPU Registers in ADL Mode
In ADL mode, the BC, DE, HL, IX and IY registers are 24 bits long for multibyte opera-
tions and indirect addressing. The most significant bytes (MSBs) of these 3 multibyte reg-
isters are designated with a U to indicate the upper byte. For example, the upper byte of
multibyte register BC is designated BCU. Thus, the 24-bit BC register in ADL mode is
composed of the three 8-bit registers {BCU, B, C}. Likewise, the upper byte of the IX reg-
ister is designated IXU. The 24-bit IX register in ADL mode is composed of the three 8-bit
registers {IXU, IXH, IXL}.
Note: None of the upper bytes (BCU, DEU, IXU, etc.) are individually accessible as standalone
8-bit registers.
MBASE is not used for address generation in ADL mode; however, it can only be written
in ADL mode. The Program Counter is 24 bits long, as is SPL. IEF1, IEF2, ADL, and
MADL are single bit flags.
The CPU registers and bit flags during Z80 mode operation are indicated in
4. Reset states are detailed in
UM007714-0908
16-Bit
Registers
SPS
PC
16-Bit
Registers
Or
IXL IX
IYL IY
Table 5.
eZ80
User Manual
Single-Bit Flags
ADL
MADL
IEF1
IEF2
Tables 3
Registers and Bit Flags
®
CPU
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