ZiLOG eZ80 User Manual page 236

LD r, r'
Load Register
Operation
r ← r'
Description
The r and r' operands are any of A, B, C, D, E, H, or L. The CPU writes the contents of
the r' register to the r register. The r' register described here should not be confused with
the registers in the alternate working register set.
Condition Bits Affected
None.
Attributes
Mnemonic Operand
LD
= binary code
jj
register and
object code, as indicated in
Table 70. Register and
Register jj (ddd or sss)
A
B
C
D
E
H
L
UM007714-0908
ADL Mode Cycle Opcode (hex)
X
r,r'
where
01 ddd sss
identifies the source A, B, C, D, E, H, or L register assembled in the
sss
Table 70.
Opcodes for LD r, r' Instruction (hex)
jj
111
000
001
010
011
100
101
1
jj
identifies the destination A, B, C, D, E, H, or L
ddd
®
eZ80 CPU
User Manual
227
CPU Instruction Set