ZiLOG eZ80 User Manual page 173

IND2
Input from I/O and Decrement
Operation
(HL) ← ({UU, BC[15:0]})
B ← B – 1
C ← C – 1
HL ← HL – 1
Description
The CPU places the contents of BC[15:0] onto the lower two bytes of the address bus,
ADDR[15:0]. The upper byte of the address bus, ADDR[23:16], is undefined for I/O
addresses. The CPU reads the byte located at this I/O address into CPU memory. The CPU
next places the contents of HL onto the address bus and writes the byte to the memory
address specified by the HL register. Next, the CPU decrements the B, C, and HL regis-
ters, and sets the Z Flag to 1 if the B register is decremented to 0.
Condition Bits Affected
S
Z
H
P/V
N
C
Attributes
Mnemonic Operand
IND2
IND2.S
IND2.L
UM007714-0908
Not affected.
Set if B – 1 = 0; reset otherwise.
Not affected.
Not affected.
Set if msb of data is a logical 1; reset otherwise.
Not affected.
ADL Mode Cycle Opcode (hex)
— x
— 1
— 0
5
ED, 8C
6
52, ED, 8C
6
49, ED, 8C
®
eZ80 CPU
User Manual
164
CPU Instruction Set