ZiLOG eZ80 User Manual page 336

Table 92. RST N Instruction Detail
0
1
Condition Bits Affected
None.
Attributes
Mnemonic Operand
RST n
RST.S n
RST.L n
The opcode (
the opcodes indicated in
Table 93. Restart Address and kk Opcodes for RST n Instruction (hex)
Restart
Address
00h
08h
10h
18h
20h
28h
UM007714-0908
.L The starting Program Counter is {MBASE, PC[15:0]}.
Push the 2-byte return address, PC[15:0], onto the SPL
stack. Push a 02h byte onto the SPL stack, indicating an
interrupt from Z80 mode, because ADL = 0. Set the ADL
mode bit to 1. Write {0000h, nn} to PC[23:0]. The
ending Program Counter is PC[23:0] = {0000h, nn}.
.L The starting Program Counter is PC[23:0]. Push the 3-
byte return address, PC[23:0], onto the SPL stack. Push
a 03h byte onto the SPL stack, indicating an interrupt
from ADL mode, because ADL = 1. The ADL mode bit
remains set to 1. Write {0000h, nn} to PC[23:0]. The
ending Program Counter is PC[23:0] = {0000h, nn}.
ADL Mode Cycle Opcode (hex)
n 0/1
n 1
n 0
) is a function of the 8-bit Restart Address, n, and is assembled into one of
kk
Table 93.
kk
C7
C
D7
DF
E7
EF
5/6
kk
8
52, kk
7
49, kk
®
eZ80 CPU
User Manual
327
CPU Instruction Set