ZiLOG eZ80 User Manual page 77

Table 37. Instruction Summary (Continued)
Instruction and Operation
LDD
(DE) ← (HL)
DE ← DE – 1
HL ← HL – 1
BC ← BC – 1
LDDR
repeat {
(DE) ← (HL)
DE ← DE – 1
HL ← HL – 1
BC ← BC – 1
} while BC ≠ 0
LDI
(DE) ← (HL)
DE ← DE+1
HL ← HL+1
BC ← BC – 1
LDIR
repeat {
(DE) ← (HL)
DE ← DE+1
HL ← HL+1
BC ← BC – 1
} while BC ≠ 0
LEA IX/Y, IX+d
IX/Y ← IX+d
LEA IX/Y, IY+d
IX/Y ← IY+d
LEA rr, IX+d
rr ← IX+d
LEA rr, IY+d
rr ← IY+d
Note: *This flag value is a function of the result of the affected operation.
— = No Change.
0 = Set to 0.
1 = Set to 1.
V = Set to 1 if overflow occurs.
X = Undetermined.
P = Set to the parity of the result (0 if odd parity, 1 if even parity).
IEF2 = The value of Interrupt Enable Flag 2.
UM007714-0908
Address Mode
Opcode(s)
Dest Source (Hex)
ED A8
ED B8
ED A0
ED B0
IX+d
ED 32-55
IY+d
ED 33-54
IX+d
ED 02-22
IY+d
ED 03-23
®
eZ80 CPU
User Manual
Flags Affected
S Z H P/V N C
— — 0 * 0 —
— — 0 * 0 —
— — 0 * 0 —
— — 0 * 0 —
— — — — — —
— — — — — —
— — — — — —
— — — — — —
CPU Instruction Set
68