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DI
Disable Interrupt
Operation
IEF1 ← 0
IEF2 ← 0
Description:
This instruction disables the maskable interrupts by resetting the interrupt enable flags
(IEF1 and IEF2).
Condition Bits Affected
None.
Attributes
Mnemonic
DI
UM007714-0908
Operand
ADL Mode
—
X
Cycle
Opcode (hex)
1
F3
®
eZ80
CPU
User Manual
140
CPU Instruction Set
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