Clock Inputs Display - Agilent Technologies 1660A Series User Reference

50/100-mhz state, 500-mhz timing logic analyzers
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Clock Inputs Display

Beneath the Clock Inputs display, and next to the activity indicators, is a
display of all clock inputs available in the present configuration. Depending
on the model, the number of available clocks vary. The J and K clocks
appears with pod pair 1/2, the L and M with pod pair 3/4, and clocks N and P
with pod pairs 7/8 for the 1660 and 5/6 for the 1661. In a model with more
than three pod pairs, all other clock lines are displayed to the left of the
displayed master clocks, and are used as only data channels.
With the exception of the Range resource, all unused clock bits can be used
as data channels. If any clock line is used as a data channel, the bit must be
assigned. Activity indicators above the clock identifier show clock or data
signal activity.
Clock inputs display
Clock Inputs Display
The Format Menu
Clock Inputs Display
Activity indicators
Clocks assigned as
data channels
11–13

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