Agilent Technologies 1660A Series User Reference page 180

50/100-mhz state, 500-mhz timing logic analyzers
Table of Contents

Advertisement

The Format Menu
Master and Slave Clock Field (State only)
Clock edges are ORed to clock edges, clock qualifier are ANDed to clock
edges, and clock qualifiers can be either ANDed or ORed together. All clock
and qualifier combinations on the left side of the graphic line are ORed to all
combinations on the right side of the line. For example, in a six-clock model,
all combinations of the J, K, and L clock with Q1 and Q2 qualifiers, are ORed
to the clock combinations of the M, N, and P clocks with Q3 and Q4 qualifiers.
The clock threshold level is the same as the level assigned in the Pod
Threshold field.
Clock edge selection menu
Clock Edges and Levels
11–22

Advertisement

Table of Contents
loading

This manual is also suitable for:

1660a1661a1662a1663a1664a1663as

Table of Contents