Agilent Technologies 1660A Series User Reference page 174

50/100-mhz state, 500-mhz timing logic analyzers
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The Format Menu
Pod Clock Field (State only)
Slave
This option specifies that data on a pod designated "Slave Clock" are latched
when the status of the slave clock inputs meets the requirements of the slave
clocking arrangement. Then, followed by a match of the master clock and
the master clock arrangement, the slave data is strobed into analyzer memory
along with the master data. See the figure below.
If multiple slave clocks occur between master clocks, only the data latched by
the last slave clock prior to the master clock is strobed into analyzer memory.
Pod 1
Pod 2
Master
Master
Latching Slave Data
Slave clock arrangement field
Slave Clock Field
11–16
Analyzer Memory
Slave Latch
Pod 3
Slave
Master
Clock
Slave
Clock
Pod 4
Slave

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