Agilent Technologies 1660A Series User Reference page 368

50/100-mhz state, 500-mhz timing logic analyzers
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Specifications and Characteristics
Specifications and Characteristics
Minimum Master to Slave Clock Time
Minimum Slave to Master Clock Time
Clock Qualifiers Setup/Hold
State Tagging
Counts the number of qualified states between each
[3]
stored state. Measurement can be shown relative to the previous state or
relative to trigger. Max. count is 4.29 x 10^9.
State Tag Count 0 to 4.29 x 10^9 (+/- 0 counts)
State Tag Resolution 1 count
Time Tagging
Measures the time between stored states, relative to
[3]
either the previous state or to the trigger. Max. time between states is
34.4 sec. Min. time between states is 8 ns.
Time Tag Count 8 ns to 34.3 s +/- (8 ns + 0.01% of time tag value)
Time Tag Resolution 8 ns or 0.1% (whichever is greater)
Timing Analysis
Conventional Timing
[1]
timing channels.
Maximum Timing Speed 250 MHz / 500 MHz
Channel Count
1660A 136/68
1661A 102/51
1662A 68/34
1663A 34/17
1664A 34/17
Sample Period 4 ns/2 ns minimum, 8.38 ms maximum
Memory Depth per Channel 4096/8192
Time Covered by Data Sample period x Memory depth 16.3 us min,
34.3 s/68.6 s max
19–6
0.0 ns
[2]
4.0 ns
[2]
4.0/0 ns (fixed)
[2]
Data stored at selected sample rate across all

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