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State Analysis
Maximum State Speed* 100 MHz (1660A through 1664A)
Channel Count
[1]
Memory Depth per Channel
State Clocks Six clocks are available and can be used by either one or
two state analyzers at any time. Clock edges can be ORed together and
operate in single phase, two phase demultiplexing, or two phase mixed
mode. Clock edge is selectable as positive, negative, or both edges for
each clock.
State Clock Qualifier The high or low of up to 4 of the 6 clocks can be
ANDed or ORed with the clock specification.
Setup/Hold*
one clock
[2]
one edge
one clock
both edges
multi clock
multi edge
Minimum State Clock Pulse Width*
Minimum Master to Master Clock Time*
Minimum Slave to Slave Clock Time
Specifications and Characteristics
Specifications and Characteristics
50 MHz (1664A)
1660A 136/68
1661A 102/51
1662A 68/34
1663A 34/17
1664A 34/17
4096/8192
[1]
3.5/0 ns to 0/3.5 ns
(in 0.5 ns increments)
4.0/0 ns to 0/4.0 ns
(in 0.5 ns increments)
4.5/0 ns to 0/4.5 ns
(in 0.5 ns increments)
3.5 ns
[2]
[2]
10.0 ns (1660A through 1663A)
20.0 ns (1664A)
[2]
10.0 ns (1660A through 1663A)
20.0 ns (1664A)
19–5
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