Agilent Technologies 1660A Series User Reference page 19

50/100-mhz state, 500-mhz timing logic analyzers
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1660A
8K-deep / 68
Conventional
chan. 65 data
half channel 500 MHz
3 data or clock
4K-deep / 136
Conventional
chan. 130 data
full channel 250 MHz
6 data or clock
8K-deep / 68
Transitional
chan. 65 data
half channel 250 MHz
3 data or clock
4K-deep / 136
chan. 130 data
Transitional
full channel 125 MHz
6 data or clock
4K-deep / 68
chan. 65 data
Glitch
half channel 125 MHz
3 data or clock
Introduction
Configuration Capabilities
Timing Analyzer Configurations
1661A
8K-deep / 51
chan. 48 data
+
+
3 data or clock
4K-deep / 102
chan. 96 data
+
+
6 data or clock
8K-deep / 51
chan. 48 data
+
+
3 data or clock
4K-deep / 102
chan. 96 data
+
+
6 data or clock
4K-deep / 51
chan. 48 data
+
+
3 data or clock
Timing Analyzer Configuration Considerations
Unused clock channels can be used as data channels
In Glitch half channel mode, memory is split between data and glitches.
1–6
1662A
1663A
8K-deep / 34
8K-deep / 17
chan. 32 data
chan. 16 data
+
+
2 data or clock
1 data or clock
4K-deep / 68
4K-deep / 34
chan. 64 data
chan. 32 data
+
4 data or clock
2 data or clock
8K-deep / 34
8K-deep / 17
chan. 32 data
chan. 16 data
+
+
2 data or clock
1 data or clock
4K-deep / 68
4K-deep / 34
chan. 64 data
chan. 32 data
+
4 data or clock
2 data or clock
4K-deep / 34
4K-deep / 17
chan. 32 data
chan. 16 data
+
+
2 data or clock
1 data or clock
1664A
8K-deep / 17
chan. 16 data
+
1 data or clock
4K-deep / 34
chan. 32 data
+
+
2 data or clock
8K-deep / 17
chan. 16 data
+
1 data or clock
4K-deep / 34
chan. 32 data
+
+
2 data or clock
4K-deep / 17
chan. 16 data
+
1 data or clock

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