Agilent Technologies 1660A Series User Reference page 369

50/100-mhz state, 500-mhz timing logic analyzers
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Transitional Timing
[1]
when the data changes. A time tag stored with each sample allows
reconstruction of waveform display. Time covered by a full memory
acquisition varies with the frequency of pattern changes in the data.
Maximum Timing Speed 125 MHz/250 MHz
Channel Count
1660A 136/68
1661A 102/51
1662A 68/34
1663A 34/17
1664A 34/17
Sample Period 8 ns/4 ns
Time Covered by Data 16.3 us minimum, 9.7 hrs/6.5 hrs maximum
Maximum Time Between Transitions 34.3 s
Number of Captured Transitions 1023-2047/682-4094 Depending on
input signals
Glitch Capture Mode sample period Data samples and glitch
information are stored every sample period.
Maximum Timing Speed 125 MHz
Channel Count
1660A 68
1661A 51
1662A 34
1663A 17
1664A 17
Sample Period 8 ns minimum, 8.38 ms maximum
Minimum Glitch Width 3.5 ns
Maximum Glitch Width Sample Period - 1 ns
Memory Depth per Channel 2048
Time Covered by Data Sample Period x 2048 16.3 us minimum,
17.1 s maximum
Specifications and Characteristics
Specifications and Characteristics
Sample is stored in acquisition memory only
19–7

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