Specifications
Maximum State Speed 100 MHz (1660A through 1663A)
Minimum State Clock Pulse Width
Minimum Master to Master Clock Time
Minimum Glitch Width 3.5 ns
Threshold Accuracy +/- (100 mV +3% of threshold setting)
Setup/Hold
one clock
[2]
one edge
one clock
both edges
multi clock
multi edge
Specifications and Characteristics
50 MHz (1664A)
3.5 ns
[2]
[2]
10.0 ns (1660A through 1663A)
20.0 ns (1664A)
3.5/0 ns to 0/3.5 ns
(in 0.5 ns increments)
4.0/0 to 0/4.0 ns
(in 0.5 ns increments)
4.5/0 ns to 0/4.5 ns
(in 0.5 ns increments)
Specifications
19–3