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2.5
Number of Execution States
The tables here can be used to calculate the number of states required for instruction execution.
Table 2-3 indicated the number of states required for each cycle (instruction fetch, branch
address read, stack operation, byte data access, word data access, internal operation). Table 2-4
indicates the number of cycles of each type occurring in each instruction.. The total number of
states required for execution of an instruction can be calculated from these two tables as follows:
Execution states=I×S
+J×S
I
When instruction is fetched from on-chip ROM, and an on-chip RAM is
Examples:
accessed.
1. BSET #0, @'FF00
From table 2-4:
I=L=2, J=K=M=N=0
From table 2- 3:
S
= 2, S
= 2
I
L
Number of states required for execution = 2 × 2 + 2 × 2 = 8
When instruction is fetched from on-chip ROM, branch address is read from on-chip ROM,
and on-chip RAM is used for stack area.
2. JSR @@ 30
From table 2-4:
I=2, J=K= 1, L=M=N=0
From table 2-3:
S
=S
=S
=2
I
J
K
Number of states required for execution = 2 × 2 + 1 × 2 + 1 × 2 = 8
Table 2-3. Number of States Taken by Each Cycle in Instruction Execution
Execution Status
(instruction cycle)
Instruction fetch S
I
Branch address read S
J
Stack operation S
K
Byte data access S
L
Word data access S
M
Internal operation S
N
*
Depends on which on-chip module is accessed. See the applicable hardware manual for
details.
138
+K×S
+L×S
+M×S
+N×S
J
K
L
M
Access Location
On-Chip Memory
2
N
On-Chip Peripheral Moduel
2 or 3*
1
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