Usb Jtag - Xilinx VC707 User Manual

X-Ref Target - Figure 1-6
SDIO_DAT0_LS
SDIO_DAT1_LS
SDIO_DAT2_LS
To FPGA
Bank 13 SDIO_CD_DAT3_LS
(U1)
SDIO_CMD_LS
SDIO_CLK_LS
Table 1-8
Table 1-8: SDIO Connections to the FPGA
FPGA (U1)
Schematic Net Name
Pin
AR32 SDIO_SDWP
AP32 SDIO_SDDET
AP30 SDIO_CMD_LS
AN30 SDIO_CLK_LS
AV31 SDIO_DAT2_LS
AU31 SDIO_DAT1_LS
AR30 SDIO_DAT0_LS
AT30 SDIO_CD_DAT3_LS

USB JTAG

[Figure
JTAG configuration is provided through a Digilent onboard USB-to-JTAG configuration
logic module (U26) where a host computer accesses the VC707 board JTAG chain through
a type-A (host side) to micro-B (VC707 board side) USB cable.
VC707 Evaluation Board
UG885 (v1.4) May 12, 2014
VCC1V8
51.1K 1% Six Places
0.1μF 25V
X5R
U31
TXB0108
Voltage-Level
Translator
VCCB
VCCA
A1
A2
A3
A4
A5
A6
NC
A7
NC
A8
OE
C51
0.1μF 25V
X5R
GND
Figure 1-6: SD Card Interface
lists the SD card interface connections to the FPGA.
Level Shifter (U31)
Pin Number
N/A
N/A
6
7
4
3
1
5
1-2, callout 6]
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VCC3V3
VCC3V3
51.1K 1% Six Places
C50
GND
B1
B2
B3
SDIO_CD_DAT3
B4
B5
B6
SDIO_SDDET
To FPGA
B7
Bank 12
B8
(U1)
GND
GND
VCC1V8
Pin Name
N/A
N/A
A5
A6
A3
A2
A1
A4
Feature Descriptions
VCC3V3
C52
0.1μF 25V
X5R
GND
U29
SDIO Card
Connector
4
VDD
7
SDIO_DAT0
DAT0
8
SDIO_DAT1
DAT1
9
SDIO_DAT2
DAT2
1
CD_DAT3
2
SDIO_CMD
CMD
5
SDIO_CLK
CLK
10
DETECT
IOGND2
11
SDIO_SDWP
PROTECT
IOGND1
12
NC
D_P
GNDTAB4
GNDTAB3
3
VSS1 GNDTAB2
6
VSS2 GNDTAB1
GND
UG885_c1_06_021412
SDIO Connector (U29)
Pin Number Pin Name
11 SDWP
10 SDDET
2 CMD
5 CLK
9 DAT2
8 DAT1
7 DAT0
1 CD_DAT3
Send Feedback
18
17
16
15
14
13
GND
25