Usb Jtag Module - Xilinx KC705 User Manual

Chapter 1: KC705 Evaluation Board Features

USB JTAG Module

[Figure
JTAG configuration is provided through a Digilent onboard USB-to-JTAG configuration
logic module (U59) where a host computer accesses the KC705 board JTAG chain through
a standard-A plug (host side) to micro-B plug (KC705 board side) USB cable.
A 2-mm JTAG header (J60) is also provided in parallel for access by Xilinx download cables
such as the Platform Cable USB II and the Parallel Cable IV.
The JTAG chain of the KC705 board is illustrated in
allowed at any time regardless of FPGA mode pin settings. JTAG initiated configuration
takes priority over the configuration method selected through the FPGA mode pin settings
at SW13.
X-Ref Target - Figure 1-8
USB
Module
or
JTAG
Connector
(J60)
TDO
TDI
When an FMC mezzanine card is attached to the KC705 board it is automatically added to
the JTAG chain through electronically controlled single-pole single-throw (SPST) switches
U76 and U77. The SPST switches are in a normally closed state and transition to an open
state when an FMC mezzanine card is attached. Switch U76 adds an attached FMC HPC
mezzanine card to the FPGAs JTAG chain as determined by the
FMC_HPC_PRSNT_M2C_B signal. Switch U77 adds an attached FMC HPC mezzanine
card to the FPGAs JTAG chain as determined by the FMC_LPC_PRSNT_M2C_B signal.
The attached FMC card must implement a TDI-to-TDO connection via a device or bypass
jumper for the JTAG chain to be completed to the FPGA U1.
The JTAG connectivity on the KC705 board allows a host computer to download
bitstreams to the FPGA using the Xilinx iMPACT software. In addition, the JTAG connector
allows debug tools such as the ChipScope™ Pro Analyzer or a software debugger to access
the FPGA. The iMPACT software tool can also indirectly program the Linear BPI Flash or
the Quad-SPI Flash memory. To accomplish this, the iMPACT software configures the
FPGA with a temporary design to access and program the BPI or Quad-SPI Flash memory
device. The JTAG circuit is shown in
22
1-2, callout 6]
SPST Bus Switch SPST Bus Switch
U76 U77
N.C.
J22 J2
FMC HPC FMC LPC
Connector Connector
TDI TDO TDI TDO
Figure 1-8: JTAG Chain Block Diagram
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Figure
N.C.
3.3V 2.5V
U102
SN74AVC1T45
Voltage
Translator
TDI TDO
Figure 1-9.
1-8. JTAG configuration is
U1
Kintex-7
FPGA
TDI
TDO
UG810_c1_07_120211
KC705 Evaluation Board
UG810 (v1.3) May 10, 2013