Jtag; Jtag Connection To Xc2Vp30 - Xilinx ML310 User Manual

Board Hardware

JTAG

JTAG Connection to XC2VP30

3.3V
J9 PC4
Figure 2-6: JTAG Connections to the XC2VP30 and System ACE
ML310 User Guide
UG068 (v1.01) August 25, 2004
All manuals and user guides at all-guides.com
JTAG is a simple interface that provides for many uses. On the ML310 Hardware Platform,
the primary uses include configuration of the XC2VP30, debugging software (similar to
the CPU debug interface), and debugging hardware using the ChipScope™ Integrated
Logic Analyzer (ILA).
The Virtex-II Pro family is fully compliant with the IEEE Standard 1149.1 Test Access Port
and Boundary-Scan Architecture. The architecture includes all mandatory elements
defined in the IEEE 1149.1 Standard. These elements include the Test Access Port (TAP),
the TAP controller, the instruction register, the instruction decoder, the boundary-scan
register, and the bypass register. The Virtex-II Pro family also supports some optional
instructions; the 32-bit identification register, and a configuration register in full
compliance with the standard.
The JTAG connector initially connects to the System ACE chip, which passes the JTAG
connections through to the XC2VP30.
connections between the JTAG connector, System ACE, and the XC2VP30. This diagram
also shows the logic that allows the CPU JTAG debug connector (J12) to be used to access
the JTAG interface to program the XC2VP30.
2.5V
J19
PC4_TCK
0
CPU_TCK
1
PC4_TMS
0
CPU_TMS
1
PC4_TDI
0
CPU_TDI
1
PC4_TDO
0
CPU_TDO
1
JTAG_SRC_SEL
Figure 2-6 is a block diagram showing the
System ACE
U38
TCK
CFG_TCK
TMS
CFG_TMS
TDI
CFG_TDI
TDO
CFG_TDO
CFG_PROG
CFG_INIT
CF7
Mode
Pin
2.5V
J14
Schem Pg. 20
www.xilinx.com
1-800-255-7778
2.5V 2.5V
XC2VP30
U37
TCK
TMS
TDI
TDO
PROG
INIT
CFGADDR
2.5V
SW3
Schem Pg. 47
UG068_5_25_08050
R
29