Usb Jtag - Xilinx DK-V7-VC709-G User Manual

Chapter 1: VC709 Evaluation Board Features

USB JTAG

[Figure
JTAG configuration is provided solely through a Digilent onboard USB-to-JTAG
configuration logic module (U26) where a host computer accesses the VC709 board JTAG
chain through a type-A (host side) to micro-B (VC709 board side) USB cable.
The JTAG chain of the VC709 board is illustrated in
allowed at any time regardless of FPGA mode pin settings. JTAG initiated configuration
takes priority over the configuration method selected through the FPGA mode pin settings
at SW11.
X-Ref Target - Figure 1-5
USB
Module
When an FMC mezzanine card is attached to the VC709 HPC connector J35, it is
automatically added to the JTAG chain through electronically controlled single-pole
single-throw (SPST) switch U27. The SPST switch is in a normally closed state and
transitions to an open state when an FMC mezzanine card is attached. Switch U27 adds an
attached FMC mezzanine card to the FPGAs JTAG chain as determined by the
FMC_HPC_PRSNT_M2C_B signal. The attached FMC card must implement a
TDI-to-TDO connection through a device or bypass jumper for the JTAG chain to be
completed to the FPGA U1.
The JTAG connectivity on the VC709 board allows a host computer to download
bitstreams to the FPGA using the Xilinx tools. In addition, the JTAG connector allows
debug tools or a software debugger to access the FPGA. The Xilinx tools can also indirectly
program the linear BPI flash memory. To accomplish this, the Xilinx tools configure the
FPGA with a temporary design to access and program the BPI memory device.
26
Send Feedback
1-2, callout 4]
JTAG Chain
FMC HPC1
TDI TDO
Figure 1-5: JTAG Chain Block Diagram
www.xilinx.com
Figure 1-5. JTAG configuration is
3.3V 1.8V
Voltage
TDI
Translator
TDO
Voltage
Translator
VC709 Evaluation Board
UG887 (v1.4) December 4, 2014
FPGA
U1
UG887_c1_05_100912