Ddr Memory; Ddr Dimm - Xilinx ML310 User Manual

Board Hardware
X8
SYACE_FPGA_CLK
OSC
33MHz
X7
J20
OSC
156.25
MHz
J17
X9
J21
OSC
125MHz
PM IO
DDR
DIMM
64 bit
256MB

DDR Memory

DDR DIMM

ML310 User Guide
UG068 (v1.01) August 25, 2004
All manuals and user guides at all-guides.com
II Pro FPGA I/O can be configured to use different IO standards such as SSTL2 as required
on the DDR DIMM interface. Please review the ML310 Virtex-II Pro data sheet for more
information regarding I/O standards.
Figure 2-3 shows the top-level clocking for the ML310 board.
SYSACE LCD
LVDS_CLK_LOC_P
LVDS_CLK_LOC_N
USER_SMA_CLK
7P 6S
BANK 0
12
2.5V
2.5V
LVDS
(6 LVDS)
DCM
X0Y1
BANK 7
2.5V
Note:
All 3 DDR
Clock nets
are length
matched
DDR_CLK
DDR_CLKB
BANK 6
2.5V
DCM
X0Y0
BANK 5
2.5V
7S 6P
OSC
X6
Figure 2-3: Top-Level Clocking
The ML310 includes a registered 256MB PC3200 Double Data Rate (DDR) Dual Inline
Memory Module (DIMM) with an industry standard 184-pin count. The DDR DIMM is
commercially available from Wintec Industries as part number W4F232726HA-5Q. The
associated datasheet is provided on the ML310 CDROM. The DDR DIMM is
manufactured using nine Infineon HYB25D256800BT-5, 32Mx8 DDR SDRAM devices with
13-row address lines, 10-column address lines, and 4 bank select lines. Read and write
access to the Infineon devices is programmable in burst lengths of 2, 4, or 8 column
locations. The memory module inputs and outputs are compatible with SSTL2 signaling.
Serial Presence Detect (SPD) using an SMBus interface to the DDR DIMM is also
supported. Please refer to section
DIMM module's SPD EEPROM.
LEDs IIC
PM_CLK_TOP
LVDS_CLK_EXT_N
LVDS_CLK_EXT_P
5P 4S 3P 2S
BANK 1
3.0V
DCM DCM DCM
X1Y1 X2Y1 X03Y1
DCM DCM DCM
X1Y0 X2Y0 X3Y0
BANK 4
2.5V
5S 4P 3S 2P
DDR_CLK_FB
PM_CLK_BOT
CPU
TRACE
DEBUG
SYACE_FPGA_CLK
"IIC/SMBus Interface"
www.xilinx.com
1-800-255-7778
PM IO
UART
3V
SYS_CLK
(user_clk_pci)
PCI_P_CLK5
Note:
All 5 PCI
Clock nets
1P 0S
PCI_P_CLK1
are length
thru
matched
PCI_P_CLK4
PCI
BUS
BANK 2
3.0V
3.0V
BANK 3
2.5V
72
PM IO
2.5V
(36 LVDS)
LVDS
1S 0P
LVDS_CLK_EXT_P
LVDS_CLK_EXT_N
6
(3 LVDS)
PM IO
SPI
2.5V
for more details on accessing the
R
X10
OSC
100MHz
PM2
PM1
8
MGTs
(to FPGA)
21