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Chapter 1: VC709 Evaluation Board Features
Dual DDR3 Memory SODIMMs
[Figure
The memory modules at J1 and J3 are 4 GB DDR3 small outline dual-inline memory
modules (SODIMMs), providing volatile synchronous dynamic random access memory
(SDRAM) for storing user code and data.
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Each DDR3 interface is implemented across three I/O banks: 37, 38, and 39 for J1 and 31, 32
and 33 for J3. Each bank is a 1.5V high-performance bank having a dedicated DCI VRP/N
resistor connection. An external 0.75V reference V
banks 37, 39, 31, and 33. Any interface connected to these banks that requires a reference
voltage must use this FPGA voltage reference. The connections between the DDR3
memory SODIMM sockets and the FPGA are listed in
Table 1-4: DDR3 SODIMM Socket J1 Connections to the FPGA
XCVX690T (U1) Pin
A20
B19
C20
A19
A17
A16
D20
C18
D17
C19
B21
B17
A15
A21
F17
E17
D21
C21
D18
N14
14
Send Feedback
1-2, callout 2]
Part number: MT8KTF51264HZ-1G9E1 (Micron Technology)
Supply voltage: 1.5V
Datapath width: 64 bits
Data rate: Up to 1600 MT/s
Net Name
DDR3_A_A0
DDR3_A_A1
DDR3_A_A2
DDR3_A_A3
DDR3_A_A4
DDR3_A_A5
DDR3_A_A6
DDR3_A_A7
DDR3_A_A8
DDR3_A_A9
DDR3_A_A10
DDR3_A_A11
DDR3_A_A12
DDR3_A_A13
DDR3_A_A14
DDR3_A_A15
DDR3_A_BA0
DDR3_A_BA1
DDR3_A_BA2
DDR3_A_D0
www.xilinx.com
is provided for data interface
TTREF
Table 1-4
DDR3 SODIMM Memory J1
I/O Standard
Pin Number
SSTL15
SSTL15
SSTL15
SSTL15
SSTL15
SSTL15
SSTL15
SSTL15
SSTL15
SSTL15
SSTL15
SSTL15
SSTL15
SSTL15
SSTL15
SSTL15
SSTL15
SSTL15
SSTL15
SSTL15
and
Table
1-5.
Pin Number
98
A0
97
A1
96
A2
95
A3
92
A4
91
A5
90
A6
86
A7
89
A8
85
A9
107
A10/AP
84
A11
83
A12_BC_N
119
A13
80
A14
78
A15
109
BA0
108
BA1
79
BA2
5
DQ0
VC709 Evaluation Board
UG887 (v1.4) December 4, 2014
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