Dual Ddr3 Memory Sodimms - Xilinx VC709 User Manual

Table 1-3: I/O Voltage Rails (Cont'd)

Dual DDR3 Memory SODIMMs

[Figure
The memory modules at J1 and J3 are 4 GB DDR3 small outline dual-inline memory
module (SODIMMs), providing volatile synchronous dynamic random access memory
(SDRAM) for storing user code and data.
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Each DDR3 interface is implemented across three I/O banks: 37, 38, and 39 for J1 and 31, 32
and 33 for J3. Each bank is a 1.5V high-performance bank having a dedicated DCI VRP/N
resistor connection. An external 0.75V reference V
banks 37, 39, 31, and 33. Any interface connected to these banks that requires a reference
voltage must use this FPGA voltage reference. The connections between the DDR3
memory SODIMM sockets and the FPGA are listed in
Table 1-4: DDR3 SODIMM Socket J1 Connections to the FPGA
VC709 Evaluation Board
UG887 (v1.0) February 4, 2013
FPGA (U1) Bank
Bank 35
Bank 36
Bank 37
Bank 38
Bank 39
1-2, callout 2]
Part number: MT8KTF51264HZ-1G9E1 (Micron Technology)
Supply voltage: 1.5V
Datapath width: 64 bits
Data rate: Up to 1,866 MT/s
XCVX690T (U1) Pin
A20
B19
C20
A19
A17
A16
D20
C18
D17
C19
B21
B17
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Power Supply Rail Net Name
VADJ_FPGA
FMC1_VIO_B_M2C
VCC1V5_FPGA
VCC1V5_FPGA
VCC1V5_FPGA
TTREF
Table 1-4
Net Name
Pin Number
DDR3_A_A0
DDR3_A_A1
DDR3_A_A2
DDR3_A_A3
DDR3_A_A4
DDR3_A_A5
DDR3_A_A6
DDR3_A_A7
DDR3_A_A8
DDR3_A_A9
DDR3_A_A10
DDR3_A_A11
Feature Descriptions
Voltage
1.8V
Variable
1.5V
1.5V
1.5V
is provided for data interface
and Table 1-5.
SODIMM Memory J3
Pin Number
98 A0
97 A1
96 A2
95 A3
92 A4
91 A5
90 A6
86 A7
89 A8
85 A9
107 A10/AP
84 A11
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