Ddr3 Memory - Xilinx VC707 User Manual

Chapter 1: VC707 Evaluation Board Features

DDR3 Memory

[Figure
The memory module at J1 is a 1 GB DDR3 small outline dual-inline memory module
(SODIMM). It provides volatile synchronous dynamic random access memory (SDRAM)
for storing user code and data.
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The DDR3 interface is implemented across I/O banks 37, 38, and 39. Each bank is a 1.5V
high-performance bank having a dedicated DCI VRP/N resistor connection. An external
0.75V reference VTTREF is provided for data interface banks 37 and 39. Any interface
connected to these banks that requires a reference voltage must use this FPGA voltage
reference. The connections between the DDR3 memory and the FPGA are listed in
Table
Table 1-4: DDR3 Memory Connections to the FPGA
14
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1-2, callout 2]
Part number: MT8JTF12864HZ-1G6G1 (Micron Technology)
Supply voltage: 1.5V
Datapath width: 64 bits
Data rate: Up to 1,600 MT/s
1-4.
FPGA (U1)
Net Name
Pin
A20 DDR3_A0
B19 DDR3_A1
C20 DDR3_A2
A19 DDR3_A3
A17 DDR3_A4
A16 DDR3_A5
D20 DDR3_A6
C18 DDR3_A7
D17 DDR3_A8
C19 DDR3_A9
B21 DDR3_A10
B17 DDR3_A11
A15 DDR3_A12
A21 DDR3_A13
F17 DDR3_A14
E17 DDR3_A15
D21 DDR3_BA0
C21 DDR3_BA1
D18 DDR3_BA2
N14 DDR3_D0
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J1 DDR3 Memory
Pin Number Pin Name
98 A0
97 A1
96 A2
95 A3
92 A4
91 A5
90 A6
86 A7
89 A8
85 A9
107 A10/AP
84 A11
83 A12_BC_N
119 A13
80 A14
78 A15
109 BA0
108 BA1
79 BA2
5 DQ0
VC707 Evaluation Board
UG885 (v1.4) May 12, 2014