Ddr3 Memory Module - Xilinx AC701 User Manual

Chapter 1: AC701 Evaluation Board Features

DDR3 Memory Module

[Figure
The memory module at J1 is a 1 GB DDR3 small outline dual-inline memory module
(SODIMM). It provides volatile synchronous dynamic random access memory (SDRAM)
for storing user code and data. The SODIMM socket has a perforated EMI shield
surrounding it as seen in
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The DDR3 interface is implemented across I/O banks 32, 33, and 34. Each bank is a 1.5V
high-performance (HP) bank. An external 0.75V reference VTTREF is provided for data
interface banks 32 and 34. Any interface connected to these banks that requires a reference
voltage must use this FPGA voltage reference. The connections between the DDR 3
memory and the FPGA are listed in
Table 1-4: DDR3 Memory Connections to the FPGA
12
1-2, callout 2]
Figure
Part number: MT8JTF12864HZ-1G6G1 (Micron Technology)
Supply voltage: 1.5V
Datapath width: 64 bits
Data rate: Up to 1,600 MT/s
U1 FPGA Pin Net Name
M4 DDR3_A0
J3 DDR3_A1
J1 DDR3_A2
L4 DDR3_A3
K5 DDR3_A4
M7 DDR3_A5
K1 DDR3_A6
M6 DDR3_A7
H1 DDR3_A8
K3 DDR3_A9
N7 DDR3_A10
L5 DDR3_A11
L7 DDR3_A12
N6 DDR3_A13
L3 DDR3_A14
K2 DDR3_A15
N1 DDR3_BA0
M1 DDR3_BA1
H2 DDR3_BA2
AB6 DDR3_D0
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1-2.
Table 1-4.
J1 DDR3 Memory
Pin Number
98
97
96
95
92
91
90
86
89
85
107
84
83 A12_BC_N
119
80
78
109
108
79
5
Pin Name
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A13
A14
A15
BA0
BA1
BA2
DQ0
AC701 Evaluation Board
UG952 (v1.2) August 28, 2013