How Does It Work; The Tap Controller; The Instruction Register; The Data Registers - Xilinx EZTag User Manual

Introduction
that have been implemented (in addition to all the mandatory opera-
tions of the standard and some optional ones) in the FastFLASH
family.

How does it work

The top level schematic of the test logic defined by IEEE Std 1149.1
includes three key blocks:

The TAP Controller

This responds to the control sequences supplied through the test
access port (TAP) and generates the clock and control signals
required for correct operation of the other circuit blocks.

The Instruction Register

This shift register-based circuit is serially loaded with the instruction
that selects an operation to be performed.

The Data Registers

These are a bank of shift register based circuits. The stimuli required
by an operation are serially loaded into the data registers selected by
the current instruction. Following execution of the operation, results
can be shifted out for examination.
The JTAG Test Access Port (TAP) contains four pins that drive the
circuit blocks and control the operations specified. The TAP facilitates
the serial loading and unloading of instructions and data. The four
pins of the TAP are: TMS, TCK, TDI and TDO. The function of each
TAP pin is as follows:
TCK - this pin is the JTAG test clock. It sequences the TAP controller
as well as all of the JTAG registers provided in the XC95108.
TMS - this pin is the mode input signal to the TAP Controller. The
TAP controller is a 16-state FSM that provides the control logic for
JTAG. The state of TMS at the rising edge of TCK determines the
sequence of states for the TAP controller. TMS has an internal pull-up
resistor on it to provide a logic 1 to the system if the pin is not driven.
TDI -this pin is the serial data input to all JTAG instruction and data
registers. The state of the TAP controller as well as the particular
instruction held in the instruction register determines which register
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