Intel Agilex Configuration User Manual page 139

4. Remote System Update (RSU)
UG-20205 | 2019.10.09
Command Code
(Hex)
37
QSPI_SEND_DEVICE_
OP
5D
RSU_NOTIFY
Table 36. CONFIG_STATUS and RSU_STATUS Major Error Code Descriptions
Major Error Code
0xF001
BITSTREAM_ERROR
0xF002
HARDWARE_ACCESS_FAILURE
0xF003
BITSTREAM_CORRUPTION
0xF004
INTERNAL_ERROR
0xF005
DEVICE_ERROR
(9)
This number does not include the command and response header.
Send Feedback
Command Response
(9) (9)
Length Length
To erase a sector of a Micron 2 gigabit (Gb) flash at address 0x04FF0000 using the
QSPI_WRITE_DEVICE_REG
here:
Header: 0x00003036
Opcode: 0x000000DC
Number of bytes to write: 0x00000004
Flash address: 0x0000FF04
A successful write returns the OK response code. This command pads data that is not a multiple
of 4 bytes to the next word boundary.
1 0 Sends a command opcode to the quad SPI. Takes one argument:
• The opcode to send the quad SPI device.
A successful command returns the OK response code.
1 0 Clears all error information in the
word argument has the following fields:
• 0x00050000: Clear current reset retry counter. Resetting the current retry counter sets the
counter back to zero, as if the current image was successfully loaded for the first time.
• 0x00060000: Clear error status information.
• All other values are reserved.
This command is not available before version 19.3 of the Intel Quartus Prime Pro Edition
Software.
Error Type
Potential unsigned bitstream used. Ensure the bitstream is signed with the correct key.
Failure to communicate to PMBus-compliant voltage regulator. Check your power management and
smart voltage identification (SmartVID) parameter settings and PMBus interface connections.
Bitstream is corrupt. Ensure the bit stream in configuration device or flash is not corrupt.
This major code may indicate the following error events:
• An error in the SDM Crypto IP task.
• An RSU operation error. Refer to
Indicates an SDM internal device error. The following errors are possible:
Description
command, write the flash address in MSB to LSB order as shown
response and resets the retry counter. The one-
RSU_STATUS
Description
Table 37 on page 140 for more information.
Intel ® Agilex
continued...
™ Configuration User Guide
139