Intel Agilex Configuration User Manual page 17

2. Intel Agilex Configuration Details
UG-20205 | 2019.10.09
The SDM drives Intel Agilex device configuration.
Initial Configuration Timing
The first section of the figure shows the expected timing for initial configuration after a normal power-on reset. Initially, the
application logic drives the
reflects the current configuration state.
When an error occurs,
reconfiguration.
The numbers in the Initial Configuration part of the timing diagram mark the following events:
1. The SDM boots up and samples the
not sample the
2. With the
nCONFIG
Note: For Avalon-ST x16 and x|32 configuration schemes the host must drive
If the host fails to drive
3. When the external host drives
high, signaling the beginning of FPGA configuration. The SDM receives the configuration bitstream on the interface that
the bus specified in Step 1 The diagram shows
MSEL
AVST_READY
4. The SDM drives the
5. When the Intel Agilex device asserts
impedance state. The time between the assertion of
INIT_DONE
configuration, the HPS application controls the time between
until after the software running on the HPS such as U-Boot or the operating system (OS) initiates the configuration, the
FPGA configures and enters user mode..
The entire device does not enter user mode simultaneously. Intel requires you to include the
on page 23 in your design. Use the
in the reset state until the entire FPGA fabric is in user mode. Failure to include this IP in your design may result in
intermittent application logic failures.
Send Feedback
signal low. Under normal conditions
nCONFIG
nCONFIG
pulses low for approximately 1 ms and asserts high when the device is ready to accept
nSTATUS
signals to determine the specified FPGA configuration scheme. The SDM does
MSEL
pins again until the next power cycle.
MSEL
signal low, the SDM enters Idle mode after booting.
low until it samples
nCONFIG
signal high, the SDM initiates configuration. The SDM drives the
nCONFIG
to deassert which would require
signal high, indicating the SDM received the bitstream successfully.
CONF_DONE
INIT_DONE
asserts after initialization of the FPGA fabric, including registers and state machines. For HPS first
nINIT_DONE
nSTATUS
must only change when it has the same value as
low there is a chance that configuration may fail.
nSTATUS
and
AVST_READY AVST_VALID
to deassert within six cycles.
AVST_VALID
to indicate the FPGA has entered user mode. GPIO pins exit the high
and
CONF_DONE INIT_DONE
and
CONF_DONE
output of the Reset Release Intel FPGA IP to hold your application logic
follows because
nCONFIG nSTATUS
.
nSTATUS
low until it samples
nCONFIG nSTATUS
nSTATUS
continuously high. It is possible for
is variable. For FPGA First configuration,
. does not assert
INIT_DONE INIT_DONE
Reset Release Intel FPGA IP
Intel ® Agilex ™ Configuration User Guide
low.
signal
17