Intel Agilex Configuration User Manual page 42

Signal Name
MSEL[2:0]
(5)
CONF_DONE
AVSTx8_READY
AVST_READY
AVSTx8_DATA[7:0]
AVSTx8_VALID
AVSTx8_CLK
AVST_DATA[31:0]
AVST_VALID
AVST_CLK
Refer to the Intel Agilex Data Sheet for configuration timing estimates.
The x16 and x32 modes use GPIO pins that only support the 1.2 V I/O standard. The SDM I/O pins require a 1.8 V power
supply. Consequently, you may need a voltage-level translation between the FPGA and external host because some signals, to
accommodate both power requirements.
Note: Although the
INIT_DONE
The SDM drives the
debugging configuration.
Note: If you create custom logic instead of using the PFL II IP to drive configuration, refer to the Avalon Streaming Interfaces in the
Avalon Interface Specifications for protocol details.
Related Information
• Avalon Interface Specifications
• Intel Agilex Device Data Sheet
(5)
is required if you are using the Intel FPGA Parallel Flash Loader II IP as the configuration host.
CONF_DONE
Intel ® Agilex ™ Configuration User Guide
42
Pin Type
SDM I/O, Dual-Purpose
SDM I/O
SDM I/O
GPIO, Dual-Purpose
SDM I/O
SDM I/O
SDM I/O
GPIO, Dual-Purpose
GPIO, Dual-Purpose
GPIO, Dual-Purpose
configuration signal is not required for configuration, Intel recommends that you use this signals.
signal high to indicate the device is fully in user mode. This signal is important when
INIT_DONE
3. Intel Agilex Configuration Schemes
UG-20205 | 2019.10.09
Direction Powered by
Input
Output
Output
Output
Input
Input
Input
Input
Input
Input
V
CCIO_SDM
V
CCIO_SDM
V
CCIO_SDM
V
CCIO
V
CCIO_SDM
V
CCIO_SDM
V
CCIO_SDM
V
CCIO
V
CCIO
V
CCIO
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