Intel Agilex Configuration User Manual page 85

3. Intel Agilex Configuration Schemes
UG-20205 | 2019.10.09
Pin
fpga_pgm[]
fpga_conf_done
fpga_nstatus
pfl_nreconfigure
pfl_flash_access_request
flash_addr[]
flash_data[]
flash_nce[]
(7)
Intel recommends that you do not insert logic between the PFL II pins and the host I/O pins, especially on the
pins.
fpga_nconfig
Send Feedback
Type Weak Pull-Up
Input —
Input 10 kΩ Pull-Up
Resistor
Input 10 kΩ Pull-Up
Resistor
Input —
Output —
Output —
Input or Output —
(bidirectional pin)
Output —
Function
Determines the page for the configuration. This pin is not available if you
are only using the PFL II IP for flash programming.
Connects to the pin of the FPGA. The FPGA releases the pin
CONF_DONE
high if the configuration is successful. During FPGA configuration, this pin
remains low. This pin is not available if you are only using the PFL II IP for
flash programming.
Connects to the pin of the FPGA. This pin is high before the
nSTATUS
FPGA configuration begins and must stay high during FPGA configuration.
If a configuration error occurs, the FPGA pulls this pin low and the PFL II
IP core stops reading the data from the flash memory device. This pin is
not available if you are only using the PFL II IP for flash programming.
When low initiates FPGA reconfiguration. To implement manual control of
reconfiguration connect this pin to a switch. You can use this input to write
your own logic in a CPLD to trigger reconfiguration via the PFL II IP. You
can use to drive the
pfl_nreconfigure
initiating reconfiguration. The
pfl_clk
not available if you are only using the PFL II IP for flash programming.
For system-level synchronization. When necessary, this pin connects to a
processor or an arbiter. The PFL II IP core drives this pin high when the
JTAG interface accesses the flash or the PFL II IP configures the FPGA.
This output pin works in conjunction with the
pins.
The flash memory address. The width of the address bus depends on the
density of the flash memory device and the width of the
Intel recommends that you turn On the Set flash bus pins to tri-state
when not in use option in the PFL II .
Bidirectional data bus to transmit or receive 8-, 16-, or 32-bit data. Intel
recommends that you turn On the Set flash bus pins to tri-state when
(7)
not in use option in the PFL II.
Connects to the pin of the flash memory device. A low signal enables
nCE
the flash memory device. Use this bus for multiple flash memory device
support. The pin connects to each
flash_nce
connected flash memory devices. The width of this port depends on the
number of flash memory devices in the chain.
Intel
output signal
fpga_nconfig
pin registers this signal. This pin is
and
flash_noe flash_nwe
bus.
flash_data
pin of all the
nCE
continued...
and
flash_data
® Agilex ™ Configuration User Guide
85