Intel Agilex Configuration User Manual page 92

Figure 36. Connections for AS Configuration with Multiple Serial Flash Devices
V
CCIO_SDM
Optional
Monitoring
Config AS x4 Memory
FPGA
Image (.rpd)
HPS AS x4 Memory
HPS Data
Intel ® Agilex ™ Configuration User Guide
92
Configuration
10kΩ
Control Signals
10kΩ
nCONFIG
nSTATUS
CONF_DONE
INIT_DONE
Optional
OSC_CLK_1
3
MSEL MSEL[2:0]
Configuration
Data Signals
4
AS_DATA[3:0]
DATA[3:0]
AS_CLK
DCLK
AS_nCS0[0]
CS
HPS Data Signals
DATA[3:0]
AS_nCS0[1]
DCLK
AS_nCS0[2]
AS_nCS0[3]
CS
TCK
TDO
To JTAG Header
or JTAG Chain TMS
TDI
Intel FPGA
V
R
UP
Download cable 10 pin male header (JTAG mode)
JTAG
Configuration
Pins
3. Intel Agilex Configuration Schemes
UG-20205 | 2019.10.09
CCIO_SDM
R
UP
Pin 1
TCK GND
TDO VCCIO_SDM
TMS OPEN
OPEN OPEN
TDI GND
3M Part number : 2510-6002UB
Send Feedback
R
DN
G
ND