Intel Agilex Configuration User Manual page 24

Figure 7. Reset Release Intel FPGA IP INIT_DONE External Connection
If you do not include the Reset Release Intel FPGA IP in your design, you must feed the
design as an input to your reset logic as shown in this figure.
Intel ® Agilex ™ Configuration User Guide
24
Intel FPGA
INIT_DONE
Reset
Application Logic
2. Intel Agilex Configuration Details
UG-20205 | 2019.10.09
signal back into your
INIT_DONE
Board
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