Intel Agilex Configuration User Manual page 117

3. Intel Agilex Configuration Schemes
UG-20205 | 2019.10.09
3.4.2.2. JTAG Single-Device Configuration using a Microprocessor
Refer to the Intel Agilex Device Family Pin Connection Guidelines for additional information about individual pin usage and
requirements.
Figure 51. Connection Setup for JTAG Single-Device Configuration using a Microprocessor
V
CCIO_SDM
R R
UP UP
Send Feedback
Optional
Monitoring
Pin 1
R
DN
TCK GND
TDO VCCIO_SDM
TMS OPEN
OPEN OPEN
TDI GND
G
ND
V V
CCIO_SDM CCIO_SDM
Configuration
10kΩ
Control Signals
10kΩ
Optional
3
MSEL
Micro Processor
TCK
TDO
JAM
TMS
Player
TDI
ADDR DATA
Memory
Intel FPGA
nCONFIG
nSTATUS
CONF_DONE
INIT_DONE
OSC_CLK_1
MSEL[2:0]
TCK
JTAG
TDO
Configuration
TMS
Pins
TDI
Intel ® Agilex ™ Configuration User Guide
117