Intel Agilex Configuration User Manual page 51

3. Intel Agilex Configuration Schemes
UG-20205 | 2019.10.09
Figure 15. Connections for Avalon-ST x32 Single-Device Configuration
External Host
Send Feedback
CPLD / FPGA
fpga_nconfig
fpga_nstatus
fpga_conf_done
Parallel Flash Loader II IP
or
Microprocessor
or
Custom Logic
fpga_data [31:0]
fpga_valid
fpga_ready
fpga_clk
Compact Flash Interface
ADDR DATA Control
External Compact Flash Memory
.rbf
(little endian)
V
CCIO_SDM
V
CCIO_SDM
Configuration
10kΩ
Control Signals
10kΩ
nCONFIG
nSTATUS
CONF_DONE
INIT_DONE
OSC_CLK_1
(1) (2)
3
MSEL[2:0]
MSEL
32
AVST_DATA [31:0]
AVST_VALID
AVST_READY
AVST_CLK
Configuration
Data Signals
External Clock Source (Optional)
Intel FPGA
Intel ® Agilex ™ Configuration User Guide
51