Intel Agilex Configuration User Manual page 84

Options
Time period before the —
watchdog timer times
out
Use advance read • Normal mode
mode?
• Intel Burst mode
• 16 byte page mode (GL only)
• 32 byte page mode (MT23EW)
• Micron Burst Mode (M58BW)
Latency count • 3
• 4
• 5
3.1.10.4. PFL II Signals
Table 22. PFL II Signals
Pin
pfl_nreset
pfl_flash_access_granted
pfl_clk
Intel ® Agilex ™ Configuration User Guide
84
Value
Specifies the time out period for the watchdog timer. The default time out period is 100
ms.
This option improves the overall flash access time for the read process during the FPGA
configuration.
• Normal mode—applicable for all flash memory
• Intel Burst mode—Applicable for devices that support bursting. Reduces sequential
read access time
• 16 byte page mode (GL only)—applicable for Cypress GL flash memory only
• 32 byte page mode (MT23EW)—applicable tor MT23EW only
• Micron Burst Mode (M58BW)—applicable for Micron M58BW flash memory only
For more information about the read-access modes of the flash memory device, refer to
the respective flash memory data sheet.
Specifies the latency count for Intel Burst mode.
Type Weak Pull-Up
Input —
Input —
Input —
3. Intel Agilex Configuration Schemes
Description
Function
Asynchronous reset for the PFL II IP core. Pull high to enable FPGA
configuration. To prevent FPGA configuration, pull low when you do not
use the PFL II IP core. This pin does not affect the PFL II IP flash
programming functionality.
For system-level synchronization. A processor or any arbiter that controls
access to the flash drives this input pin. To use the PFL II IP core function
as the flash master pull this pin high. Driving the
pin low prevents the JTAG interface from
pfl_flash_access_granted
accessing the flash and FPGA configuration.
User input clock for the device. This is the frequency you specify for the
What is the external clock frequency? parameter on the Configuration
tab of the PFL II IP. This frequency must not be higher than the maximum
frequency you specify for FPGA during configuration. This pin is not
DCLK
available if you are only using the PFL II IP for flash programming.
UG-20205 | 2019.10.09
continued...
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