Intel Agilex Configuration User Manual page 120

An falling edge terminates any JTAG access and the device reverts to the
nCONFIG
must be stable during JTAG configuration.
must be stable.
Unlike other configuration schemes,
the error messages that the Intel Quartus Prime Pro Edition Programmer generates for error reporting.
Note: For Intel Agilex SX devices when you choose to configure the FPGA fabric first, the JTAG chain has no mechanism to redeliver
the HPS boot information following a cold reset. Consequently, you must reconfig the device with the
resets to continue operation.
Debugging Suggestions
Here are some debugging tips for JTAG:
• Verify that the JTAG pin connections are correct.
• If JTAG configuration is failing, check that the FPGA has successfully powered up and exited POR. One strategy is to check
the hand shaking behavior between
goes low.
•
Verify that the
• Another way to determine whether the device has exited the POR state is to use the Intel Quartus Prime Programmer to
detect the device. If the programmer can detect the Intel Agilex device, it has exited the POR state.
• If you are using an Intel FPGA Download Cable II, reduce the cable clock speed to 6 MHz.
• If you have multiple devices in the JTAG chain, try to disconnect other devices from the JTAG chain to isolate the Intel
Agilex device.
•
If you specify the
you specify in the Intel Quartus Prime software.
• For designs including the High Bandwidth Memory (HBM2) IP or any IP using transceivers, you must provide a free
running and stable reference clock to the device before device configuration begins. All transceiver power supplies must
be at the required voltage before configuration begins.
• When you use the JTAG interface for reconfiguration after an initial reconfiguration using AS or the Avalon-ST interface,
the must be in the file format you specified in the Intel Quartus Prime project. For example, if initially configure the
.sof
pins for AS configuration and configure using the AS scheme, a subsequent JTAG reconfiguration using a
MSEL
generated for Avalon-ST fails.
Intel ® Agilex ™ Configuration User Guide
120
nSTATUS
does not assert if an error occurs during JTAG configuration. You must monitor
nSTATUS
nCONFIG
pin remains high during JTAG configuration.
nCONFIG
as the clock source for configuration, ensure that
OSC_CLK_1
follows during JTAG configuration. Consequently,
nCONFIG
and by driving
nSTATUS nCONFIG
3. Intel Agilex Configuration Schemes
UG-20205 | 2019.10.09
-specified boot source.
MSEL nCONFIG
nCONFIG
file or avoid cold
.sof
low and ensuring that
nSTATUS
is running at the frequency
OSC_CLK_1
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also
also
.sof