Intel Agilex Configuration User Manual page 96

Figure 39. AS Programming Using Intel Quartus Prime or Third-Party Programmer
Intel ® Agilex ™ Configuration User Guide
96
AS x4 Flash
DATA0
DATA1
DATA2
DATA3
DCLK
nCS
V
CCIO_SDM
10 kΩ
10 kΩ
Intel FPGA
nSTATUS
nCONFIG
CONF_DONE
AS_DATA[0]
AS_DATA[1]
AS_DATA[2]
AS_DATA[3]
AS_CLK
V
CCIO_SDM
OSC_CLK_1
4.7 kΩ
MSEL [0]/AS_nCSO[0]
MSEL [1]
MSEL [2]
V
CCIO_SDM
AS fast/normal mode: Pull MSEL [2] low
JTAG mode: Pull MSEL [2] high
AS fast mode: Pull MSEL [1] low
GND AS normal mode: Pull MSEL [1] high
3. Intel Agilex Configuration Schemes
UG-20205 | 2019.10.09
External clock source
to is optional.
Send Feedback