Intel Agilex F Series User Manual
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Intel Agilex F Series User Manual

Intel Agilex F Series User Manual

Fpga (two f-tiles) development kit
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Intel
Agilex
F-Series FPGA (Two
F-Tiles) Development Kit User Guide
ID:
739942
Online Version
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Version:
2022.09.21

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Summary of Contents for Intel Agilex F Series

  • Page 1 ® ™ Intel Agilex F-Series FPGA (Two F-Tiles) Development Kit User Guide 739942 Online Version Send Feedback Version: 2022.09.21...

  • Page 2: Table Of Contents

    5.2. Active Serial (AS) x4 Configuration Mode..............28 5.3. Avalon-ST x16 Configuration Mode................. 28 6. Custom Projects for the Development Kit..............30 6.1. Add SmartVID Settings in the Intel Quartus Prime QSF File........30 6.2. Golden Top......................30 7. Revision History......................31 A.
  • Page 3 A.2. FPGA Configuration....................36 A.2.1. Programming the FPGA over On-Board Intel FPGA Download Cable II..... 37 A.2.2. Programming the FPGA over an External Intel FPGA Download Cable II... 37 A.3. Default Switch and Jumper Settings............... 37 A.3.1. Switch Description................... 38 A.3.2.

  • Page 4: Overview

    Intel's standard warranty, but reserves the right to make changes to any 9001:2015 products and services at any time without notice. Intel assumes no responsibility or liability arising out of the Registered application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel.

  • Page 5: Feature Summary

    — 1x PCIe/CXL interface supporting x4 interface connected to MCIO connector • Memory interfaces ™ — Two x72 DIMM sockets supporting DDR4-2666 or DDR-T Intel Optane persistent memory module — Single x40 DDR4 component interface for HPS processor memory •...

  • Page 6: Box Contents

    — Two slots height with heatsink/fan assembly • Operating environment — Maximum ambient temperature of 0-35°C 1.3. Box Contents • Intel Agilex F-Series (Two F-Tiles)FPGA Development Kit • 1x DDR4 DIMM module • 1x IO48 HPS daughter board • USB 2.0 MicroUSB cable •...

  • Page 7: Getting Started

    Intel's standard warranty, but reserves the right to make changes to any 9001:2015 products and services at any time without notice. Intel assumes no responsibility or liability arising out of the Registered application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel.
  • Page 8 Design Examples: Memory, XCVR, GPIO, PCIe Gen 4 Contains the original data programmed onto the board factory_recovery before shipment. Use this data to restore the board with its original factory content. ® ™ Intel Agilex F-Series FPGA (Two F-Tiles) Development Kit User Guide Send Feedback...

  • Page 9: Power Up The Development Kit

    Intel's standard warranty, but reserves the right to make changes to any 9001:2015 products and services at any time without notice. Intel assumes no responsibility or liability arising out of the Registered application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel.

  • Page 10: Applying Power To The Development Board

    Intel MAX 10 JTAG_EN switch. • ON sets the JTAG pins to function as dual-purpose I/O pins and JTAG function if the JTAG pin sharing option bit is enabled by the Intel Quartus Prime software. • OFF sets the JTAG pins to function as JTAG dedicated pins if the JTAG pin sharing option bit is enabled by the Intel Quartus Prime software (Default).
  • Page 11 FPGA's SDM interface. When the configuration is complete, green LED (D12) illuminates signaling the device configured successfully. If the configuration fails, D12 will not illuminate. ® ™ Intel Agilex F-Series FPGA (Two F-Tiles) Development Kit User Guide Send Feedback...

  • Page 12: Board Test System

    Intel's standard warranty, but reserves the right to make changes to any 9001:2015 products and services at any time without notice. Intel assumes no responsibility or liability arising out of the Registered application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel.

  • Page 13: Download Openjdk

    JavaFX Version 4.1.3. Install OpenJDK and OpenJFX You have two downloaded zip files, follow these steps to install them. 1. On Windows system, Intel recommends you to unzip the files and put them in the following directory: — C:\Program Files\Java\jre ®...

  • Page 14: Install The Intel Quartus Prime Software

    You have the following two directories on your Linux system: — /opt/Java/jre — /opt/Java/jfx 4.1.4. Install the Intel Quartus Prime Software You need to install the Intel Quartus Prime software that can support the silicon on the development kit. The recommended version can be found in the file README.txt under directory.
  • Page 15 1. On Windows system, double click the .bat files to run BTS, Clock Controller, or Power Monitor GUI. Figure 6. Windows Console 2. On Linux system, you need to run the shell script with root privilege. ® ™ Intel Agilex F-Series FPGA (Two F-Tiles) Development Kit User Guide Send Feedback...

  • Page 16: Test The Functionality Of The Development Kit

    4.2. Test the Functionality of the Development Kit This section describes each control in the BTS. 4.2.1. The Bottom Info Bar The bottom information bar shows the status of the system connection, the Intel Quartus Prime version and the JTAG clock. •...

  • Page 17: The Sys Info Tab

    3. When configuration finishes, the design begins running in the FPGA. The corresponding GUI application tabs that interface with the design are now enabled. If you use the Intel Quartus Prime Programmer for configuration, instead of the BTS GUI, you need to restart the GUI.

  • Page 18: The Gpio Tab

    JTAG Chain The JTAG chain control shows all the devices currently in the JTAG chain. Note: Both System Intel MAX 10 and FPGA must be in the JTAG chain when running the BTS GUI. 4.2.4. The GPIO Tab The GPIO tab allows you to interact with all the general-purpose user I/O components on your board.

  • Page 19: The Xcvr Tab

    • Detail: Shows the PLL lock and pattern sync status of each channel. The number of the error bits of each channel can be found here. ® ™ Intel Agilex F-Series FPGA (Two F-Tiles) Development Kit User Guide Send Feedback...
  • Page 20 Select the following available data types for analysis: • PRBS7: pseudo-random 7-bit binary sequences • PRBS15: pseudo-random 15-bit binary sequences • PRBS23: pseudo-random 23-bit binary sequences • PRBS31: pseudo-random 31-bit binary sequences (default) ® ™ Intel Agilex F-Series FPGA (Two F-Tiles) Development Kit User Guide Send Feedback...
  • Page 21 Data Rate: Displays the XCVR type and data rate of each channel. Figure 13. QSFP NRZ - Data Rate 4.2.5.2. The QSFP PAM4 Tab Similar control functions with the QSFP NRZ tab. ® ™ Intel Agilex F-Series FPGA (Two F-Tiles) Development Kit User Guide Send Feedback...
  • Page 22 Similar control functions with the QSFP NRZ tab. Figure 15. The QSFPDD NRZ Tab 4.2.5.4. The QSFPDD PAM4 Tab Similar control functions with the QSFP NRZ tab. ® ™ Intel Agilex F-Series FPGA (Two F-Tiles) Development Kit User Guide Send Feedback...

  • Page 23: The Memory Tab

    Download the design through BTS Configure. Figure 17. The RDIMM1 Tab The following sections describe controls on this tab. Start Initiates DDR4 memory transaction performance analysis. Stop Terminates transaction performance analysis. ® ™ Intel Agilex F-Series FPGA (Two F-Tiles) Development Kit User Guide Send Feedback...
  • Page 24 Insert error is only enabled during transaction performance analysis. • Clear: Resets the Detected Errors counter and Inserted Errors counter to zeros. Figure 18. The RDIMM2 Tab Similar with RDIMM1. ® ™ Intel Agilex F-Series FPGA (Two F-Tiles) Development Kit User Guide Send Feedback...

  • Page 25: Control On-Board Clock Through Clock Controller Gui

    Sets the programmable oscillator frequency for the selected clock to the value in the output controls for ZL30733. Frequency changes might take several milliseconds OUTx to take effect. You might see glitches on the clock during this time. Intel recommends resetting the FPGA logic after changing frequencies. ®...

  • Page 26: Monitor On-Board Power Regulator Through Power Monitor Gui

    PCB. The Power Monitor GUI communicates with system Intel MAX 10 through a 10-pin JTAG header J3 or USB port J10. System Intel MAX 10 monitors and controls power regulator, temperature/voltage/current sensing chips through a 2-wire I C bus.

  • Page 27: Bts Test Areas

    Plug the DDR4 DIMM module which is shipped alone with this development kit in J4/J5. BTS GUI only supports fabric memory interfaces, namely DDR4 DIMM1 and DDR4 DIMM2. ® ™ Intel Agilex F-Series FPGA (Two F-Tiles) Development Kit User Guide Send Feedback...

  • Page 28: Development Kits Hardware And Configuration

    Intel's standard warranty, but reserves the right to make changes to any 9001:2015 products and services at any time without notice. Intel assumes no responsibility or liability arising out of the Registered application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel.
  • Page 29 J105 Notes Image 0 Installed Installed Image 0—Default Image 1 Open Installed Image 1 Image 2 Installed Open Image 2 Image 3 Open Open Image 3 ® ™ Intel Agilex F-Series FPGA (Two F-Tiles) Development Kit User Guide Send Feedback...

  • Page 30: Custom Projects For The Development Kit

    Intel's standard warranty, but reserves the right to make changes to any 9001:2015 products and services at any time without notice. Intel assumes no responsibility or liability arising out of the Registered application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel.

  • Page 31: Revision History

    Intel's standard warranty, but reserves the right to make changes to any 9001:2015 products and services at any time without notice. Intel assumes no responsibility or liability arising out of the Registered application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel.

  • Page 32: Development Kit Components

    Intel's standard warranty, but reserves the right to make changes to any 9001:2015 products and services at any time without notice. Intel assumes no responsibility or liability arising out of the Registered application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel.
  • Page 33 Intel MAX 10 JTAGEN switch Enables Intel MAX 10 to use the JTAG pins as I/Os. CPU RESETn Sends an active low signal to the FPGA and Intel MAX 10 which can be used as the RESET for internal designs. HPS RESETn Sends an active low signal to the Intel MAX 10.
  • Page 34 739942 | 2022.09.21 Board Reference Type Description Red over temperature LED LED is on when the Intel MAX 10 detects an over-temperature condition on the board. Green FPGA CONF_DONE LED LED is on when the FPGA is successfully configured. D[11:D8] 4 green user LEDs FPGA connected LEDs for user designs.
  • Page 35 Table 14. Communication Ports Board Reference Type Description 10-pin JTAG header For connecting an external Intel FPGA Download Cable II dongle. Micro-USB connector For connecting to the on-board Intel FPGA Download Cable II. Table 15. Miscellaneous Ports Board Reference Type...

  • Page 36: Intel Max 10 Cpld System Controller

    Fan control • Clock control A.2. FPGA Configuration You can use the Intel Quartus Prime Programmer to configure the FPGA with your SRAM Object File (.sof). Ensure the following: • The Intel Quartus Prime Programmer and the Intel FPGA Download Cable II driver are installed on the host computer.

  • Page 37: Programming The Fpga Over On-Board Intel Fpga Download Cable Ii

    A. Development Kit Components 739942 | 2022.09.21 Using the Intel Quartus Prime Programmer to configure a device on the board causes other JTAG based applications such as the Board Test System and the Power Monitor to lose their connection to the board. Restart those applications after configuration is complete.

  • Page 38: Switch Description

    Default Position ON for PCIe x16 ON for PCIe x8 ON for PCIe x4 ON for PCIe x1 Table 18. SW2—Single DIP for Intel FPGA Download Cable II Selection Switch position Board Label Function Default Position USB MAX JTAG SEL...

  • Page 39: Jumper Description

    In Avalon-ST x16 configuration mode, the board provides one QSPI flash for storing up to four configuration images. Configuration of the FPGA with one of these images is managed by the Intel MAX 10, depending on the selection of jumpers J105 and J106. ®...

  • Page 40: Input And Output Components

    A.4. Input and Output Components A.4.1. Push Buttons The Intel Agilex FPGA (two F-tiles) development board includes several dedicated push buttons for you. When you press and hold down the button, the device pin is set to logic 0. When you release the button, the device pin is set to logic 1. There are no board-specific functions for these general user push buttons.

  • Page 41: Leds

    Intel Agilex FPGA device. A.5.1. PCI Express (PCIe) Interface The Intel Agilex FPGA (two F-tiles) development board is designed to fit entirely into a PC motherboard with a x16 PCI Express slot that can accommodate a full height, 2- slot, ¾...
  • Page 42 The PCI Express interface supports auto-negotiating channel width from x1 to x4 to x8 to x16 by using PCIe Intel FPGA IP. You can also configure this board to a x1, x4, x8, or x16 interface through a DIP switch that connects the...
  • Page 43 Transmit bus PCIE_EP_RX_N1 1.4 V PCML Transmit bus PCIE_EP_RX_N2 1.4 V PCML Transmit bus PCIE_EP_RX_N3 1.4 V PCML Transmit bus PCIE_EP_RX_N4 1.4 V PCML Transmit bus continued... ® ™ Intel Agilex F-Series FPGA (Two F-Tiles) Development Kit User Guide Send Feedback...

  • Page 44: Qsfp-Dd Interface

    The Intel Agilex FPGA (two F-tiles) development board includes a connector and cages system for mounting a Double Density Quad Small Form-Factor Pluggable (QSFP-DD) module. The interface connects to eight 56 Gbps PAM4 capable F-tile lanes of the Intel Agilex FPGA, supporting QSFP-DD modules, with capability of 400 Gbps aggregate bandwidth with power classifications up to 10 W.
  • Page 45 QSFPDD_RX7_P True Differential Signaling QSFPDD Receive Channel 7 Positive QSFPDD_RX7_N True Differential Signaling QSFPDD Receive Channel 7 negative QSFPDD_REFCLK_P AD48 LVPECL QSFPDD Reference Clock Positive continued... ® ™ Intel Agilex F-Series FPGA (Two F-Tiles) Development Kit User Guide Send Feedback...

  • Page 46: Qsfp Interface

    QSFP modules, with capability of 200 Gbps aggregate bandwidth with power classifications up to 3.5 W. Table 31. QSFP Pin Assignments For more information about Intel's True Differential Signaling technology, refer to the Intel Agilex Device Data Sheet. Schematic Signal Name FPGA Pin Number...

  • Page 47: Cxl Interface

    The Intel Agilex FPGA (two F-tiles) development board provides a CXL connector interface for cabling to an Intel-designed M.2 SSD daughter card supporting M-Keying. This interface connects to four 28 Gbps F-tile lanes of the Intel Agilex FPGA. When connecting the development board to this SSD daughter card, the development board connects four transceiver channels from the F-tile bank 12C to M2 channels 8-11 (J5) of the M.2 daughter card.

  • Page 48: Ddr4 Dimm1 Interface

    The Intel Agilex FPGA (two F-tiles) development board provides two DDR4 x72 DIMM interfaces connected to the FPGA fabric. DIMM1 is connected to the Intel Agilex I/O96 of banks 2C and 2D. Only one DIMM memory module is included with the development kit for evaluation of the DDR4 interfaces.
  • Page 49 1.2 V HS LVCMOS DDR4 DIMM1 DQ34 data DDR4_DIMM1_DQ35 DJ27 1.2 V HS LVCMOS DDR4 DIMM1 DQ35 data DDR4_DIMM1_DQ36 DE23 1.2 V HS LVCMOS DDR4 DIMM1 DQ36 data continued... ® ™ Intel Agilex F-Series FPGA (Two F-Tiles) Development Kit User Guide Send Feedback...
  • Page 50 1.2 V HS LVCMOS DDR4 DIMM1 Data Strobe Negative for byte lane 6 DDR4_DIMM1_DBI_N6 CY22 1.2 V HS LVCMOS DDR4 DIMM1 Data Bus Inversion for byte lane 6 continued... ® ™ Intel Agilex F-Series FPGA (Two F-Tiles) Development Kit User Guide Send Feedback...
  • Page 51 DDR4 DIMM1 Bank Address 0 DDR4_DIMM1_A17 CV24 1.2 V HS LVCMOS DDR4 DIMM1 Address 17 DDR4_DIMM1_A16 CR27 1.2 V HS LVCMOS DDR4 DIMM1 Address 16 continued... ® ™ Intel Agilex F-Series FPGA (Two F-Tiles) Development Kit User Guide Send Feedback...

  • Page 52: Ddr4 Dimm2 Interface

    The Intel Agilex FPGA (two F-tiles) development board provides two DDR4 x72 DIMM interfaces connected to the FPGA fabric. DIMM2 is connected to the Intel Agilex I/O96 of banks 2E and 2F. Only one DIMM memory module is included with the development kit for evaluation of the DIMM interfaces.
  • Page 53 1.2 V HS LVCMOS DDR4 DIMM2 DQ20 data DDR4_DIMM2_DQ21 CT52 1.2 V HS LVCMOS DDR4 DIMM2 DQ21 data DDR4_DIMM2_DQ22 CN53 1.2 V HS LVCMOS DDR4 DIMM2 DQ22 data continued... ® ™ Intel Agilex F-Series FPGA (Two F-Tiles) Development Kit User Guide Send Feedback...
  • Page 54 DDR4_DIMM2_TDQS_N13 CR51 1.2 V HS LVCMOS DDR4 DIMM2 Termination Data Strobe for byte lane 4 DDR4_DIMM2_DQ40 CY50 1.2 V HS LVCMOS DDR4 DIMM2 DQ40 data continued... ® ™ Intel Agilex F-Series FPGA (Two F-Tiles) Development Kit User Guide Send Feedback...
  • Page 55 1.2 V HS LVCMOS DDR4 DIMM2 DQ62 data DDR4_DIMM2_DQ63 DH50 1.2 V HS LVCMOS DDR4 DIMM2 DQ63 data DDR4_DIMM2_DQS_P7 DH48 1.2 V HS LVCMOS DDR4 DIMM2 Data Strobe continued... ® ™ Intel Agilex F-Series FPGA (Two F-Tiles) Development Kit User Guide Send Feedback...
  • Page 56 1.2 V HS LVCMOS DDR4 DIMM2 Address 8 DDR4_DIMM2_A7 DE37 1.2 V HS LVCMOS DDR4 DIMM2 Address 7 DDR4_DIMM2_A6 DF36 1.2 V HS LVCMOS DDR4 DIMM2 Address 6 continued... ® ™ Intel Agilex F-Series FPGA (Two F-Tiles) Development Kit User Guide Send Feedback...

  • Page 57: Ddr4 Component Interface

    DDR4 DIMM2 Bank Group 1 A.5.7. DDR4 Component Interface The Intel Agilex FPGA (two F-tiles) development board provides a DDR4 x40 Interface comprised of five DDR4 x8 components for HPS access. This gives 32-bits data plus 8- bits ECC, which are connected to I/O96 of bank 3D.
  • Page 58 DDR4 component DQS 3 strobe negative DDR4_COMP_DBI_N3 1.2 V HS LVCMOS DDR4 component Data Bus Inversion for byte lane 3 DDR4_COMP_DQ32 1.2 V HS LVCMOS DDR4 component DQ32 data continued... ® ™ Intel Agilex F-Series FPGA (Two F-Tiles) Development Kit User Guide Send Feedback...
  • Page 59 1.2 V HS LVCMOS DDR4 DIMM2 Clock Negative DDR4_COMP_CK_P 1.2 V HS LVCMOS DDR4 DIMM2 Clock Positive DDR4_COMP_CKE 1.2 V HS LVCMOS DDR4 Component Clock Enable continued... ® ™ Intel Agilex F-Series FPGA (Two F-Tiles) Development Kit User Guide Send Feedback...

  • Page 60: Hps I/O48 Interface

    The Intel Agilex FPGA (two F-tiles) development board connects the 48 HPS I/Os ) to a mezzanine connector for installing the HPS_IOA[24:1] HPS_IOB[24:1] Intel HPS I/O48 daughter card. This daughter card provides the HPS with USB, UART, Ethernet, SD card, I C, and JTAG accessibility. Table 36.
  • Page 61 C for reading and writing to the various components on the board such as programmable clock generators, voltage regulators, temperature sensors, and EEPROMs. You can use the Intel Agilex or Intel MAX 10 as the I C host to access these devices, change clock frequencies, or get board status information such as the voltage and temperature readings.
  • Page 62 Temp Sense PCIe (EU1) Gold Finger (J1) MAX31730 ADDR=9Ah Temp Sense (EU2) Table 37. Intel MAX 10 I C Signals Schematic Signal Name MAX Pin Number I/O Standard Description MAX_I2C_SCL 3.3 V open drain Intel MAX 10 I C clock MAX_I2C_SDA 3.3 V open drain...

  • Page 63: Intel Max 10 Spi Bus

    A. Development Kit Components 739942 | 2022.09.21 A.7. Intel MAX 10 SPI Bus The Intel MAX 10 device uses the SPI bus for reading telemetry information from the Analog Devices LTC3888 VCC core controller. Table 39. SPI Signals Schematic Signal Name...

  • Page 64: Hps Daughter Card

    Configuration clock A.9. HPS Daughter Card The development kit includes an Intel HPS daughter card that mounts to a Samtec 48- pin connector (J6) and connects to the Intel Agilex HPS I/O 48 bank. The HPS daughter card provides SoC port functionality to the development kit. These ports include Ethernet, USB, UART, I C, JTAG, and a SD memory card slot.
  • Page 65 Ethernet TX Data0 HPS_GPIO17 AN13 1.8 V LVCMOS Ethernet TX Data1 HPS_GPIO18 AG11 1.8 V LVCMOS Ethernet RX Data0 HPS_GPIO19 AP14 1.8 V LVCMOS Ethernet RX Data1 continued... ® ™ Intel Agilex F-Series FPGA (Two F-Tiles) Development Kit User Guide Send Feedback...

  • Page 66: System Power

    Ethernet MDC A.10. System Power This section describes the Intel Agilex FPGA development board's power supply. A laptop style DC power supply is provided with the development kit. Use only the supplied power supply. The power supply has an auto sensing input voltage of 100 –...

  • Page 67: Power Guidelines

    A. Development Kit Components 739942 | 2022.09.21 Power telemetry is provided via the Intel MAX 10 and I C interface to the various voltage regulators and temperature sensors on the board. The power utilization is displayed on a GUI that shows power consumption versus time.

  • Page 68: Power Distribution System

    A. Development Kit Components 739942 | 2022.09.21 Figure 29. As a Standalone Evaluation Board Powered by Included Power Supply A.12. Power Distribution System The following figure shows the power distribution system on the Intel Agilex FPGA development board. Figure 30. Power Tree 3.3V...

  • Page 69: Power Measurement

    Intel MAX 10 system controller for power telemetry data reporting. The V rail for the FPGA core power is measured by the Intel MAX 10 using the SPI bus interface between the Intel MAX 10 and VCC core controller. The Intel MAX 10 provides power data through the Power Monitor GUI.

  • Page 70: Additional Information

    Intel's standard warranty, but reserves the right to make changes to any 9001:2015 products and services at any time without notice. Intel assumes no responsibility or liability arising out of the Registered application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel.

  • Page 71: Safety Warnings

    To avoid shock, you must ensure that the power cord is connected to a properly wired and grounded receptacle. Ensure that any equipment to which this product is attached to is also connected to properly wired and grounded receptacles. ® ™ Intel Agilex F-Series FPGA (Two F-Tiles) Development Kit User Guide Send Feedback...

  • Page 72: Safety Cautions

    Certain components such as heat sinks, power regulators, and processors may be hot. Heatsink fans are not guarded. Power supply fan may be accessible through guard. Care should be taken to avoid contact with these components. ® ™ Intel Agilex F-Series FPGA (Two F-Tiles) Development Kit User Guide Send Feedback...
  • Page 73 Public Switched Telecommunication Network (PSTN) as it might result in disruption of the network. No formal telecommunication certification to FCC, R&TTE Directive, or other national requirements have been obtained. ® ™ Intel Agilex F-Series FPGA (Two F-Tiles) Development Kit User Guide Send Feedback...
  • Page 74 Failure to use wrist straps can damage components within the system. Attention: Please return this product to Intel for proper disposition. If it is not returned, refer to local environmental regulations for proper recycling. Do not dispose of this product in unsorted municipal waste.

  • Page 75: Compliance Information

    B. Additional Information 739942 | 2022.09.21 Please return this product to Intel for proper disposition. If it is not returned, refer to local environmental regulations for proper recycling. Do not dispose of product in unsorted municipal waste. B.2. Compliance Information...

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