Intel Agilex Configuration User Manual page 87

3. Intel Agilex Configuration Schemes
UG-20205 | 2019.10.09
Note: The serial flash configuration device must be fully powered up at the same time or before ramping up V
Agilex device.
The AS configuration scheme supports AS x4 (4-bit data width) mode only.
Table 23. Intel Agilex Configuration Data Width, Clock Rates, and Data Rates
Mode
Active Active Serial (AS)
Table 24. Required Configuration Signals for the AS Configuration Scheme
You specify SDM I/O pin functions using the Device
reassign the GPIO, dual-purpose configuration pins for other functions in user mode.
Configuration Function
nSTATUS
nCONFIG
MSEL[2:0]
CONF_DONE
AS_nCSO[3:0]
AS_DATA[3:0]
AS_CLK
Note:
Although the
CONF_DONE
signals. The SDM drives the
signal high to indicate the device is fully in user mode.These signals are important when debugging configuration.
INIT_DONE
You can reassign the GPIO, dual-purpose configuration pins for other functions in user mode.
MSEL Pin Function for the AS x4 Configuration Scheme
The SDM samples the
the pins become active-low chips selects. For AS x4 designs using one flash device,
MSEL
remaining chip select pins,
Send Feedback
Data Width (bits)
4
Configuration
Pin Type
SDM I/O
SDM I/O
SDM I/O, Dual-Purpose
SDM I/O
SDM I/O
SDM I/O
SDM I/O
and configuration signals are not required, Intel recommends that you use these
INIT_DONE
signal high after successfully receiving full bitstream. The SDM drives the
CONF_DONE
pins immediately after power-on in the SDM Start state. After the SDM samples the
MSEL
- deassert high.
AS_nCS1 AS_nCS3
Max Clock Rate Max Data Rate
133 MHz
Device and Pin Options dialog box in the Intel Quartus Prime software. You can
Direction
Output
Input
Input
Output
Output
Bidirectional
Output
of the Intel
CCIO_SDM
MSEL[2:0]
Fast mode - 001
532 Mb
Normal mode - 011
Powered by
V
CCIO_SDM
V
CCIO_SDM
V
CCIO_SDM
V
CCIO_SDM
V
CCIO_SDM
V
CCIO_SDM
V
CCIO_SDM
pins,
MSEL
asserts low. The
AS_nCSO
Intel ® Agilex ™ Configuration User Guide
87